Key Engineering Materials, ISSN: 1662-9795, Vol. 1024, pp 23-28

doi: 10.4028/p-yA5cwi

© 2025 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2024-09-20

Revised:
2025-08-28

Accepted:
2025-08-28

Online:
2025-09-12

Achieving Low , Competitive Performance and Enhanced Post-Stress Flatband Voltage Stability Using Deposited Oxide

The original version of this paper is available on https://www.scientific.net/KEM.1024.23.pdf

Umesh Chand , Chien Yu-Chieh , Abdul Hannan Yeo , Voo Qin Gui Roth , Shiv Kumar , Akhil Ranjan , Binni Varghese , Weijie Wang , Pavan Vudumula , Tamara Fidler , Patrick Schmid , Mario Saggio , Maurizio Castorina , Marco Camalleri , Jia Xie , Gong Xiao , Surasit Chung , Lakshmi Kanta Bera , Navab Singh , Yeo Yee Chia

Institute of Microelectronics (IME), Agency for Science, Technology and Research (A*STAR), Singapore 138634

Centrotherm International AG, Blaubeuren, Germany

STMicroelectronics, Singapore & Catania, Italy

National University of Singapore, Singapore

chand_umesh@a-star.edu.sg, Chien_Yu_Chieh@a-star.edu.sg,

cHannan_Yeo@a-star.edu.sg, Roth_Voo@a-star.edu.sg,

shiv_kumar@ime.a-star.edu.sg, Ranjan_Akhil@a-star.edu.sg, Binni_Varghese@a-star.edu.sg,

Wang_Weijie@a-star.edu.sg, ivudumulapk@ime.astar.edu.sg, jtamara.fidler@centrotherm.de,

patrick.schmid@centrotherm.de, mario.saggio@st.com, maurizio.castorina@st.com,

marco.camalleri@st.com, ojiaweix@u.nus.edu, elegong@nus.edu.sg,

surasit_chung@ime.a-star.edu.sg, 'lakshmi_kanta_bera@ime.a-star.edu.sg,

navab@ime.a-star.edu.sg, yeo_yee_chia@hq.a-star.edu.sg

Keywords: Deposited Oxide, Interface Trap Density, Flat Band Voltage, and Reliability.

Abstract

In this work, we propose and experimentally validate a novel approach to achieve superior interface properties of the MOS capacitors through a low-temperature oxide deposition technique for gate dielectric followed by a nitridation process. Low interface trap density ( ), robust flat-band voltage stability under positive bias stress, and decent leakage current density ( ) can be unambiguously verified after nitric oxide (NO) gas postdeposition annealing.

Introduction

The original version of this paper is available on https://www.scientific.net/KEM.1024.23.pdf

Silicon carbide (SiC) power MOSFETs are a key enabling technology in high-efficiency power electronics applications, particularly in systems requiring high voltage, high temperature, and high switching frequency. Despite their promise, one of the primary challenges SiC MOSFETs faces is their inherently low channel mobility, which limits overall device performance[1,2]. This issue is largely attributed to the high interface trap density (Dit) at the interface, primarily caused by carbon-related defects formed during the high-temperature oxidation process to create the gate dielectric layer [2,3]. These defects introduce unwanted energy states within the bandgap, which act as traps, reducing the mobility of carriers and thereby degrading the on-state performance of the device.

Various strategies have been explored to mitigate these challenges, including modifications to the oxidation process and post-oxidation annealing treatments. Traditional oxidation methods at high temperatures often result in significant carbon contamination at the SiC interface, increasing the density of interface traps. Low-temperature deposition techniques have recently emerged as a promising alternative. These methods offer better control over the interface properties, reducing carbon-related defects and thus improving channel mobility [4,5]. However, despite the advantages,
the precise impact on long-term device reliability and performance remains an open area of research. A deeper understanding of the interface engineering under these conditions is crucial to unlocking the full potential of SiC MOSFETs.

In this work, we explore the effectiveness of a low-temperature deposited oxide as a gate dielectric in mitigating interface-related challenges in SiC MOSFET technology. Our results show that the deposited oxide approach yields a minimal of , excellent device-to-device uniformity, decent leakage current density ( ), and superior flat-band voltage stability ( ) under positive bias stress.

Fig. 1. Fabrication process flow for the MOS capacitors.

Fig. 1. Fabrication process flow for the MOS capacitors.

Result and Discussion

The original version of this paper is available on https://www.scientific.net/KEM.1024.23.pdf

MOS capacitors were fabricated on a highly doped n-type off-cut (0001) substrate, with a thick nitrogen-doped homo-epilayer. Key aspects of the process flow are illustrated in Fig. (1). High-resolution transmission electron microscopy (HRTEM) images were obtained for all the samples to investigate the presence of an additional layer at the interface following post-oxidation/deposition annealing (POA/PDA). A sharp interface can be seen between and SiC [Fig. 2(a-b)]. To access device yield and uniformity, we randomly selected 15 devices of the same die and measured [Fig. 3(a)]. The tight statistical distribution of for randomly selected devices is shown in Fig. 3(b). Capacitance-voltage ( ) measurement was conducted to investigate the impact of different methods on the interface [Fig. 3(c-f)]. The oxide-4 devices significantly reduce to [Fig. 4(a)], which may be attributed to the effective mitigation of carbon-related defects in deposited oxide, and the incorporation of nitrogen may further passivate dangling bonds at the interface after NO POA. The tight distribution with small coefficient of variation ( ) is observed for [Fig. 4(b)]. X-ray photoelectron spectroscopy (XPS) study supported the existence of a slightly nitrogen-rich SiC surface after NO POA/PDA [Fig. 4(c)].

Fig. 2. (a-d) Cross-sectional TEM of the interface for all the samples.

Fig. 2. (a-d) Cross-sectional TEM of the interface for all the samples.

Fig. 3. (a) for the MOS capacitors and (b) statistical distribution of for randomly selected devices and (c-f) quasi static and curves of the MOS capacitors.

Fig. 3. (a) for the MOS capacitors and (b) statistical distribution of for randomly selected devices and (c-f) quasi static and curves of the MOS capacitors.

Next, the measurements were repeated from -5 V to various accumulation voltages from 5 V to 25 V [Fig. 5(a-d)] to investigate the effect of high accumulation voltage on flat-band ( ) stability. The improved stability for the oxide-4 devices could be due to the reduction of interface defects and near interface traps at the interface. Furthermore, we examined the stability by conducting a positive bias stress test. The oxide field ( ) is applied according to industry guidelines to ensure accurate and reliable testing procedures [10]. A constant voltage stress corresponding to values of 3,5 , and was applied for a duration of up to [Fig. 5(e-h)]. The bulk trap density ( ) extracted as a function of bias stress time with various values of 3, 5 , and shown in Fig. 6(a-d). The oxide-4 scheme device manifests superior stability against bias stress with the lowest extracted .

Fig. 4. (a) energy distribution of estimated by the high-low method [2], (b) the distribution of extracted at around , and (c) nitrogen concentration plotted for for all samples.

Fig. 4. (a) energy distribution of estimated by the high-low method [2], (b) the distribution of extracted at around , and (c) nitrogen concentration plotted for for all samples.

Fig. 5. (a-d) curves with different accumulation voltages of the MOS capacitors and (e-h) as a function of bias stress time with various of 3,5 , and .

Fig. 5. (a-d) curves with different accumulation voltages of the MOS capacitors and (e-h) as a function of bias stress time with various of 3,5 , and .

This can be attributed to the minimization of carbon-related defects through the deposited oxide approach, in which the trap states are further reduced by NO-PDA. Finally, we benchmark the and of our devices with previously reported deposited oxide SiC devices (Table I). It is reasonable to conclude that the oxide-4 device in this study has achieved the lowest and a satisfactory value ( ).

Fig. 6. (a-d) as a function of bias stress time with various field of 3,5 , and . (e) change in plotted as a function of nitrogen concentration and Table-1 Benchmark of this work with reported work.

Fig. 6. (a-d) as a function of bias stress time with various field of 3,5 , and . (e) change in plotted as a function of nitrogen concentration and Table-1 Benchmark of this work with reported work.

Conclusion

The original version of this paper is available on https://www.scientific.net/KEM.1024.23.pdf

In summary, our deposited gate oxide on SiC with NO-POA had produced low and led to a significant enhancement in MOS capacitor device performance and reliability such as superior stability under positive bias stress.

Acknowledgement

The original version of this paper is available on https://www.scientific.net/KEM.1024.23.pdf

This work was supported by the Science and Engineering Research Council of A*STAR (Agency for Science, Technology, and Research) Singapore, under Grant No. A20H9a0242.

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The original version of this paper is available on https://www.scientific.net/KEM.1024.23.pdf

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