Key Engineering Materials, ISSN: 1662-9795, Vol. 1024, pp 79-86

doi: 10.4028/p-0t5ifB

© 2025 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2024-09-20

Revised:
2025-08-27

Accepted:
2025-08-27

Online:
2025-09-12

Fabrication of -SiC Low Gain Avalanche Detectors (LGADs)

The original version of this paper is available on https://www.scientific.net/KEM.1024.79.pdf

Ben J. Sekely , Yashas Satapathy , Tao Yang , Greg Allion , Philip Barletta , Steve Holland , Stefania Stucci , Carl Haber , Spyridon Pavlidis , John F. Muth

¹Department of Materials Science and Engineering, North Carolina State University, Engineering Bldg I, 911 Partners Way, Raleigh, 27606, NC, U.S

Department of Electrical and Computer Engineering, North Carolina State University, 2410 Campus Shore Dr, Raleigh, 27606, NC, U.S

Physics Division, Lawrence Berkeley National Laboratory, 1 Cyclotron Rd, Berkeley 94720, CA, U.S

NCSU Nanofabrication Facility, North Carolina State University, 2410 Campus Shore Dr, Raleigh, 27606, NC, U.S

Brookhaven National Laboratory, 98 Rochester St, Upton, 11973, NY, U.S

seholland@lbl.gov, stucci@bnl.gov, chhaber@lbl.gov, spavlidis@ncsu.edu, muth@ncsu.edu

Keywords: LGAD, PiN Diode, Particle Detection, High Energy Physics, Radiation.

Abstract

Low gain avalanche detectors (LGADs) offer high temporal resolution for high energy particle detection, which is critical for next generation experiments in hadron colliders. While silicon LGADs (Si-LGADs) have rapidly matured in the last decade, research into silicon carbide (SiC) LGADs has only recently begun. By accounting for fundamental differences in material properties and fabrication processes, we present a prototype device design and process flow for LGADs with etch-based isolation. Critical steps of the process flow and their results are discussed, including plasma etching, passivation, and the formation of low resistivity contacts. Electrical characterization (I-V, C-V) shows sufficient depletion of the device structure to demonstrate low-gain charge carrier multiplication.

Introduction

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In high energy hadron colliders, such as the High Luminosity Large Hadron Collider (HL-LHC), and possible future colliders, events contain increasingly large numbers of minimum ionizing particles (MIPs), with significant overlap of many simultaneous collisions in close proximity. Present tracking systems, based upon highly segmented silicon pixels or strips lack the timing resolution required to separate these events. Next generation collider detectors, now in preparation, will contain new fast timing devices, referred to as Silicon Low Gain Avalanche Detectors (Si-LGADs) with timing resolution in the range , but with limited spatial resolution. Si-LGADs offer better time resolution than current pixels and strips. This is due to thinner drift regions allowing charge carriers to quickly travel across the device and signal amplification through the use of an avalanche mechanism [1].

Si-based detectors are however susceptible to bulk radiation damage effects and consequently must be operated at temperatures around requiring complex, bulky, and expensive cooling systems.

The 2019 Department of Energy Basic Research Needs for High Energy Physics Detector R&D identified a number of priority research directions including improved spatial resolution for fast timing, the application of new alternative materials, and reduced cooling and mass requirements [2]. In the present work we are developing LGADs to address these directions by using rather than Si .

There are several reasons to adopt 4 H silicon carbide in place of Si in LGADs. Firstly, the ionization coefficient of holes exceeds that of electrons in SiC , unlike in Si . This, combined with the fact that the saturation velocity of electrons in SiC is over twice that of holes in silicon, means that a SiC LGAD structure should be constructed with n-type drift and gain layers. Consequently, the fast signal comes from the higher mobility avalanche electron drifting back across an n -type epitaxial layer, rather than slower hole drifting across a p-type layer in the case of a Si LGAD. Additionally, the wider band gap and greater atomic displacement energy threshold of are expected to reduced the dark current and lead to a higher theoretical radiation resistance, respectively [3,4]. Moreover, the larger thermal conductivity of SiC can simplify cooling requirements and reduce system complexity. is also of interest due to its high technological maturity and large commercial availability. For all of these reasons, is an attractive polytype choice for LGAD device development.

In the following, we describe the epitaxial design and development of first generation SiC LGADs for particle detectors. Each of the fabrication steps has been characterized. The resulting LGADs and associated test structures have been electrically tested to confirm they adhere to our expectations. We note that -particle irradiation with a source using the same devices is not presented here, butm treated in a separate publication [5].

Epitaxial Design and Characterization

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These stacks were purchased as 6 " wafers from a commercial vendor with a off-axis cut. The epi-stack shown in Fig. 1 is designed to collect holes at the front-side p-type contact layer. Thicknesses and doping concentrations were determined using Synopsys TCAD simulations with the following considerations:

The nitrogen-doped ( N -doped) n-type drift region is as low doped as possible to decrease the depletion voltage and therefore operating voltage, allowing for reduced scattering of mobile charge carriers and a better timing performance. The concentration is the minimum dopant concentration that could be commercially achieved. The drift layer thickness requires a balance: a thin region achieves a better timing resolution as the carriers travel shorter distances but reduces the MIP interaction volume and generates fewer carriers, requiring a higher gain to achieve a higher signal-to-noise ratio and be read by the read-out electronics.

The N-doped gain layer must be highly doped to create a large E-field at the p-n junction to quickly sweep out generated e-h pairs as well as induce avalanching. The gain layer thickness must be thick enough to allow for carrier multiplication but thin enough to keep the device operating at low gain (10-20) [6]. Low gain is needed to amplify signals generated by MIPs since too high a gain can amplify background noise and increase event pileup that occurs when signals from multiple MIPs are too close in timing and are indistinguishable from one another.

The aluminum doped p-type layer must be highly doped to form a good metal-semiconductor contact and minimize the resistance generated carriers experience before being collected as signal. Additionally, the high p-type creates a large E-field at the p-n junction.

These stacks were epitaxially grown by a commerical vendor using metal-organic chemical vapor deposition (MOCVD) with the buffer and drift layers grown in one run, followed by the growth of the gain and p-type contact layer. A PiN diode epi-stack was grown similar to the LGAD but without the gain layer ( Fig. 1). Secondary-Ion Mass Spectroscopy (SIMS) data confirms the doping and thickness of the contact and gain layer. Doping of the drift region is low enough to be outside the detection limit. The LGAD devices were fabricated in tandem with the PiN diodes. The two are compared to demonstrate carrier multiplication in the LGAD. The controllable low-gain mechanism of these devices is shown in a separate publication [5].

Process Flow

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Device fabrication was carried out on a 1 " die from the epi-stacks shown in Fig. 1. Test structures and devices have been fabricated with the outlined process shown in Fig. 2. The device layout includes mesas of varying sizes ( ) and test structures for process testing and
electrical characterization. Additional devices are being fabricated with this process flow in epistacks with varying gain layer doping concentration to investigate the effects on avalanching behavior, but are not discussed in this paper.

Fig. 1. Thickness and doping concentration of the left: LGAD and right: PiN diode.

Fig. 1. Thickness and doping concentration of the left: LGAD and right: PiN diode.

Fig. 2. Condensed process flow for the fabrication of an LGAD in .

Fig. 2. Condensed process flow for the fabrication of an LGAD in .

There exist several fabrication challenges when processing . It is, for example, difficult to obtain smooth etched surfaces using plasma-based etch steps in with high etch rates and achieve vertical sidewalls. Reduced surface roughness can be achieved using a select gas composition and pressure during Reactive Ion Etching (RIE) to obtain an etch of minimal roughness. This allows for a better interface between a passivation layer and the etched and reduce the surface dark current from damage at the semiconductor surface. For LGADs, a good passivation strategy is important to reduce dark current and to minimize E-field enhancement at device edges and therefore avoid breakdown. Two different passivation methods were investigated: 1) plasma-enhanced chemical vapor deposition (PECVD) of silicon dioxide ( ) and 2) thermal oxidation with a subsequent thicker PECVD SiO2 layer. Devices are fabricated using each approach and the dark current is compared. Ohmic contacts are also desired in LGADs to minimize series resistance. The process for ohmic contact formation on p-type is discussed since various thickness and compositional variations of metal stacks are used for p-type SiC contacts in the literature.

Reactive Ion Etching in 4H-SiC

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Mesa etching is a relatively simple technique to control the E-field in the device. While E-field enhancement at the device edges using this approach is expected, which will reduce the expected break-down voltage of the devices, this approach is used to demonstrate initial device operation. Future implementations will target more sophisticated edge termination strategies, such as planar junction termination extensions (JTEs), which use ion implantation [1].

In this work, an etch recipe has been developed for a mesa etch of in depth in order to etch through the contact and gain layers and isolate the devices. RIE is used to etch the mesa structures and requires process refinement to achieve smooth surfaces for the required etch depth. A smooth etch surface is desired to reduce the number of surface defects that can contribute undesired leakage current paths, E-field enhancement and instability [7]. We use a photoresist mask rather
than metal since it is simple to deposit and remove. Compared to a metal mask, photoresists typically demonstrate reduced micromasking during the etch. Micromasking occurs when the etch mask is etched and redeposited on a previously exposed region, masking the region and creating a rougher etch result.

Fig. 3. AFM images of the left: unetched mesa and right: etched region.

Fig. 3. AFM images of the left: unetched mesa and right: etched region.

The gasses used are a mixture of fluoroform ( ), diatomic oxygen ( ) and argon (Ar). Fluoroform is used as a source for fluorine atoms and is primarily responsible for etching . An oxygen gas flow of demonstrates a good balance between etch rate and surface roughness in etched regions of .The RIE process of etching with fluorinated and oxygenated species is described as a combination of physical ion bombardment and a chemically reactive process. The Si -terminated face of is etched by fluorine ions while the C-terminated face is etched by both fluorine and oxygen ions [10]. Argon affects the etch process via physical bombardment, removing residual organics from the redeposited photoresist that might induce micromasking [11] and increase etch roughness.

A smooth etch result is demonstrated using atomic force microscopy (AFM) as shown in Fig. 3. The valley-to-peak heights in both cases is about 27.5 nm which indicates the etch is not roughening the silicon carbide. Using scanning electron microscopy (SEM) shown in Fig. 4, the angle of the etched mesa side walls are measured at , indicating the selectivity of the SiC to the resist mask is low, as expected when using a photoresist mask. Vertical mesas are desirable to achieve a higher breakdown voltage and can be optimized in future studies.

Device Passivation Strategies

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Device passivation is a critical step, in particular following mesa etching, to minimize surface traps capable of increasing dark current [12] or causing premature breakdown. Historically, researchers passivated devices using thermally grown [13], Plasma-Enhanced Chemical Vapor Deposition (PECVD) and SiN [14], or with combinations of thermal oxides and deposited dielectrics [7]. Given the high thermal budget available at this stage in the process, we investigated two approaches: PECVD only, and the combination of dry thermal oxidation followed by PECVD oxide.

The PECVD SiO2 was deposited using an Oxford Plasmalab 80 Plus PECVD with inlet gas con- centration of helium ( He ), nitrous oxide and silane . The oxide was deposited at a pressure and temperature of 1000 mTorr and , respectively. The alternate method consists of a thermal oxidation in a Titan II thermal oxidation chamber prior to the PECVD deposition. The sample is exposed to dry oxygen at for 5 hours. Before cooling down, the sample is annealed at the same temperature in a nitrogen environment.

Fig. 4. Cross-sectional SEM image of a mesa in the PiN diode. The sidewall and oxide thickness are measured at and 491.3 nm , respectively.

Fig. 4. Cross-sectional SEM image of a mesa in the PiN diode. The sidewall and oxide thickness are measured at and 491.3 nm , respectively.

Fig. 5. Dark current of diodes passivated using left: only a PECVD oxide film and right: thermal oxidation and PECVD oxide film.

Fig. 5. Dark current of diodes passivated using left: only a PECVD oxide film and right: thermal oxidation and PECVD oxide film.

The total oxide thickness was measured using the SEM image shown in Fig. 4 in addition to a reflectivity measurement using a Filmetrics tool model LS-DT2. The total oxide thickness is 500 nm . The PECVD oxide is 450 nm resulting in a thermal oxide thickness of 50 nm .

The effectiveness of each passivation approach was evaluated by measuring the dark current of fabricated diodes. The resulting data is shown in Fig. 5. The dark current under a reverse bias of 10 V for a PECVD passivated device is hundreds of nA . However, the dark current for a device passivated with a thermal oxidation and subsequent PECVD oxide layer does not reach 0.1 nA at a reverse bias of 110 V . While the dark current shown here is larger than some avalanching photodiodes (APDs) [15], it is comparable to others [7, 16]. Due to the reduced dark current, passivation via both thermal oxidation and PECVD are selected.

Low Resistivity Contacts

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After selectively exposing the top of the mesa by RIE of the passivation layer, metal contacts are deposited using electron beam (e-beam) evaporation on both the back-side substrate and top- side contact layer. It is important to create ohmic contacts for LGADs in order to aid charge collection, as having a Schottky barrier will act as a current limiter by preventing charge carriers from travelling through the metal-semiconductor interface. While methods to create ohmic contacts differ in the literature, it has been found that Ni - and Al -based metal stacks are commonly used in creating ohmic contacts in n-type and p-type , respectively [17, 18, 19]. In this process, is deposited as the anode and as the cathode. The Ti on the anode promotes adhesion and uniform formation of a layer during annealing [20] while the Ti in the cathode is used to create a layer post-annealing [21], reducing the Schottky barrier height (SBH) at both interfaces. The Al will further reduce the SBH by diffusing towards the surface during annealing and increasing the conductivity at the surface as Al is the p -type dopant of [22]. The n-type and p-type contacts were simultaneously annealed at
for 5 min. in a environment. Afterwards, an layer and stack were deposited using e-beam evaporation as pad contacts for probing on the anode and cathode, respectively.

Fig. 6. Left: characteristics of for anode annealed at for 5 min . in a environment. Right: I-V characteristics of cTLMs for cathode annealed at for 5 min . in a environment.

Fig. 6. Left: characteristics of for anode annealed at for 5 min . in a environment. Right: I-V characteristics of cTLMs for cathode annealed at for 5 min . in a environment.

Fig. 7. Left: I-V characteristics of a diameter LGAD. Center: C-V and Right: Inverse C-V characteristics of a diameter 4H-SiC LGAD. Figures adapted and modified from [5].

Fig. 7. Left: I-V characteristics of a diameter LGAD. Center: C-V and Right: Inverse C-V characteristics of a diameter 4H-SiC LGAD. Figures adapted and modified from [5].

Circular transmission line measurement (cTLM) structures were fabricated on the substrate and contact layer to extract specific contact resistivity. The diameter of the inner circular pad of the cTLM is and the spacing between the adjacent contacts is , and . The I-V characteristics of the cTLMs were measured using a Keithley 4200 semiconductor parameter analyzer. According to Fig. 6, the linear I-V curves indicate ohmic contact formation on the substrate. The contacts on the contact layer show a small Schottky barrier as seen by the slight non-linearity in the I-V curves in Fig. 6. For an LGAD that will be operating at high voltages between the full depletion voltage (voltage at which the entire device is depleted) and the breakdown voltage, this Schottky barrier does not pose any major issue. It should be noted that the I-V curves were approximated to be linear to calculate the specific contact resistivity for the p-type contact. Specific contact resistivities of and were calculated for the p- and n-type contacts, respectively.

Electrical Characterization

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I-V and C-V characteristics of the devices were characterized using a Keithley 2657A high voltage SMU and Keithley 4200 semiconductor parameter analyzer, respectively. A breakdown voltage of 1160 V was measured in the LGAD. To fully deplete the gain and drift layers to ensure all electron- hole pairs generated by incoming MIPs are collected, this device must operate at a bias greater than 2 kV . The high depletion voltage required is due to the thick drift region. The breakdown voltage can be increased by incorporating edge termination features in future studies.

The gain layer depletion voltage ( ) was measured to be 77 V as shown by the characteristic "step" feature in the C-V curve in Fig. 7. The doping levels of the gain and drift layers in the LGAD and PiN diode were calculated from the C-V data to be (gain layer), (LGAD drift layer), and (PiN diode drift layer). Using an abrupt 1D diode model, the thickness of the gain layer was found to be from the extracted and doping levels. The calculated doping levels and thicknesses are close to the target values.

Summary

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Critical steps in a process flow for the fabrication of a LGAD are discussed. The roughness pre- and post-RIE is shown to be similar through a comparison of AFM images. SEM confirms the etch depth, sidewall angle, and oxide thickness. The dark currents from two different passivation strategies are compared, with a thermal oxidation coupled with PECVD oxide demonstrating lower dark current which is beneficial to avoid breakdown during high voltage operation. The Ni and Al metal stacks form low resistivity contacts in n - and p -type . Electrical characterization of the devices shows the ability to sustain high voltage as well as depletion of the gain layer to demonstrate low-gain charge carrier multiplication in the LGAD structure. Radiation response testing using particles corroborates the electrical characterization results on these same devices [5]. To test how detectors withstand high radiation environments, electrical and -particle irradiation response testing will be compared before and after exposure to high fluences of radiation. The use of ion implantation for JTEs and in place of epitaxial growth is being considered for future experiments.

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The original version of this paper is available on https://www.scientific.net/KEM.1024.79.pdf

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