The backend structures of advanced VLSI (Very-Large Scale Integration) devices have become increasingly complex because of the need to combine several types of dielectric and metal layers in order to enhance device performance and/or reliability. For example, the inter-metal dielectric (IMD) stack of an aluminum-metallization device may consist of high density plasma (HDP) fluorine-doped silicate glass (FSG) for gap fill and RC-delay minimization, plus a silicon-rich oxide (SRO) cap to prevent aluminum attack from fluorine out-diffusion. Depending on the interplay between the tensile stress of the aluminum, and the typically compressive stress of the dielectric stack, the wafer may develop a large bow of either positive or negative sign. A large positive bow may negatively impact wafer handling during processing steps that use vacuum chucking, and can also lead to excessive edge polishing during tungsten and oxide chemical–mechanical planarization (CMP) steps. This paper presents a methodology to reduce final wafer bow from ~+40 to ~-10 micron by a careful selection of SRO deposition conditions to achieve a stress value that results in flatter wafers.