Design and Manufacture of Energy-Recycling Pads for Low-Power Chips
Energy-recycling output pad cells for driving adiabatic chips are designed, which have been fabricated with Chartered 0.35um process and tested. The proposed energy-recycling output pad cells include mainly bonding pads, electrostatic discharge (ESD) protection circuits, and two stage energy-recycling buffers that are used to drive the large load capacitances on chip pads. The two stage energy-recycling buffers are realized using CPAL (Complementary Pass-transistor Adiabatic Logic) and PAL-2N (pass-transistor adiabatic logic with NMOS pull-down configuration), respectively. For comparison, a conventional output pad cell is also embedded in the test chip. The function verifications and energy loss tests for the three output pad cells are carried out. The energy consumption of the proposed two energy-recycling output pad cells has large savings over a wide range of frequencies, as compared with the conventional CMOS counterparts, since the energy on large load capacitances in the chip pads can be well recycled.
W. Q. Zhang et al., "Design and Manufacture of Energy-Recycling Pads for Low-Power Chips", Key Engineering Materials, Vols. 460-461, pp. 467-472, 2011