RTS Noise of CMOS Technology


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Experiments were carried out for n-channel devices, processed in a 300 nm CMOS technology. The investigated devices have a gate oxide thickness of 6 nm and the effective interface area is AG = 1.5 m2. The RTS measurements were performed for constant gate voltage, where the drain current was changed by varying the drain voltage. The capture time constant increases with increasing drain current. The model explaining the experimentally observed capture time constant dependence on the lateral electric field and the trap position is given. From the dependence of the capture time constant c on the drain current we can calculate x-coordinate of the trap position. Electron concentration in the channel decreases linearly from the source to the drain contact. Diffusion current component is independent on the x-coordinate and it is equal to the drift current component for the low electric field. Lateral component of the electric field intensity is inhomogeneous in the channel and it has a minimum value near the source contact and increases with the distance from the source to the drain. It reaches maximum value near the drain electrode.



Edited by:

Pavel Šandera






M. Chvátal et al., "RTS Noise of CMOS Technology", Key Engineering Materials, Vol. 465, pp. 334-337, 2011

Online since:

January 2011




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