Technology Evolution for Silicon Nano-Electronics

Volume 470

doi: 10.4028/

Paper Title Page

Authors: Yuichi Setsuhara, Masaki Hashida
Abstract: An ultra-short pulse laser process is presented that is based on a photon-induced phonon excitation process for low-temperature nano-surface modification of silicon. The present methodology is based on the concept that the energy required for re-crystallization and activation of the implanted dopants is supplied to the dopant layer via a nonequilibrium adiabatic process induced by ultra-short pulse laser irradiation at room temperature. An ultra-short pulse laser beam with a pulse duration of ~ 100 femtoseconds has been used in the present work for the investigation of surface excitation features via pump-probe reflectivity measurements and for demonstrations of room-temperature re-crystallization and activation of ion-implanted silicon substrates.
Authors: Motohiro Tomita, Daisuke Kosemura, Munehisa Takei, Kohki Nagata, Hiroaki Akamatsu, Atsushi Ogura
Abstract: Global and local strained-Si samples, namely strained-Si on insulator (SSOI) wafer and a Si substrate with a patterned SiN film were each evaluated by electron backscattering pattern (EBSP). In the EBSP measurements for SSOI, biaxial tensile stresses (biaxial tensile strains and compressive strain perpendicular to the surface) were obtained, whose values were consistent with those obtained by UV-Raman spectroscopy. One-dimensional stress distributions in the Si substrate with the patterned SiN film were obtained by EBSP, UV-Raman spectroscopy with a deconvolution method, and edge force model calculation. The results were well consistent with each other. EBSP allows us to measure stress and strain in the patterned SiN sample with 150-nm wide space. Furthermore, anisotropic biaxial stress including shear stress was also obtained by EBSP.
Authors: Chia Lung Lee, Tomohiko Sugita, Koji Tatsumi, Shigeru Ikeda, Michio Matsumura
Abstract: Using a new wet process based on a catalytic reaction, pores and grooves were formed in Si using Au, Pt, or Ag as the catalyst. The diameter of the pore can be as small as 50 nm. However, to produce wiring in Si wafers, we primarily formed pores with a diameter of about 5 μm. These pores were filled with Cu by electrochemical plating, forming Cu wires developed to the wafer surface. In the process, the catalyst particles remaining at the bottom of the pore acted as seeds for the deposition of Cu and helped fill the pores without the formation of voids. In order to control the position of pores and grooves formed in Si, methods using catalytic electrodes were also developed.
Authors: Naoya Morisawa, Mitsuhisa Ikeda, Katsunori Makihara, Seiichi Miyazaki
Abstract: We have studied the effect of 1310 nm light irradiation on the charge distribution of a hybrid floating gate consisting of silicon quantum dots (Si-QDs) and NiSi Nanodots (NiSi-NDs) in MOS capacitors. The light irradiation resulted in reduced flat-band voltage shifts of the MOS capacitors in comparison to the shift in the dark. This result can be interpreted in terms of the shift of the charge centroid toward the gate side in the hybrid floating gate caused by the photoexcitation of electrons in NiSi-NDs and the subsequent electron tunneling to Si-QDs. The capacitance of the MOS capacitors at constant gate biases was modulated with pulsed light irradiation. When the light irradiation was turned off, capacitance recovered to its level in the dark, indicating that the photoexited charges were transferred between the Si-QDs and the NiSi-NDs without being emitted to the Si substrate and gate electrode.
Authors: Yan Li Pei, Tatsuro Hiraki, Toshiya Kojima, Takafumi Fukushima, Mitsumasa Koyanagi, Tetsu Tanaka
Abstract: In this work, high density and small size metal nanodots (MND) with different work-functions were fabricated as a floating gate of nonvolatile memory (NVM) devices by self-assembled nanodot deposition (SAND). The energy band engineering of NVM was demonstrated through controlling MND work-function. For single MND layer floating gate NVM, the retention time was improved by choosing high work-function MND. Furthermore, we proposed a new type NVM with a double stacked MND floating gate. Here, the high work-function MND are placed on the top layer and the low work-function MND are placed on the bottom layer. A large memory window and long retention time were obtained. However, the thermal electron excitation is dominant for the electron discharge process during retention. How to reduce the defects in MND layer is important for further improving of memory characteristics.
Authors: Osamu Nakatsuka, Shotaro Takeuchi, Yosuke Shimura, Akira Sakai, Shigeaki Zaima
Abstract: We have investigated the growth and crystalline structures of Ge1-xSnx buffer and tensile-strained Ge layers for future use in CMOS technology. We have demonstrated that strain relaxed Ge1-xSnx layers with an Sn content of 12.3% and 9.2% can be grown on Ge and Si substrates, respectively. We achieved a tensile-strain value of 0.71 % in Ge layers on a Ge0.932Sn0.068 buffer layer. We have also investigated the effects of Sn incorporation into Ge on the electrical properties of Ge1-xSnx heteroepitaxial layers.
Authors: Heiji Watanabe, Katsuhiro Kutsuki, Iori Hideshima, Gaku Okamoto, Takuji Hosoi, Takayoshi Shimura
Abstract: We demonstrated the impact of plasma nitridation on thermally grown GeO2 for the purposes of obtaining high-quality germanium oxynitride (GeON) gate dielectrics. Physical characterizations revealed the formation of a nitrogen-rich surface layer on the ultrathin oxide, while keeping an abrupt GeO2/Ge interface without a transition layer. The thermal stability of the GeON layer was significantly improved over that of the pure oxide. We also found that although the GeO2 layer is vulnerable to air exposure, a nitrogen-rich layer suppresses electrical degradation and provides excellent insulating properties. Consequently, we were able to obtain Ge-MOS capacitors with GeON dielectrics of an equivalent oxide thickness (EOT) as small as 1.7 nm. Minimum interface state density (Dit) values of GeON/Ge structures, i.e., as low as 3 x 1011 cm-2eV-1, were successfully obtained for both the lower and upper halves of the bandgap.
Authors: Tetsuji Kato, Takaya Ueda, Yuji Ohara, Jun Kikkawa, Yoshiaki Nakamura, Akira Sakai, Osamu Nakatsuka, Shigeaki Zaima, Eiji Toyoda, Kouji Izunome, Yasuhiko Imai, Shigeru Kimura, Osamu Sakata
Abstract: The use of Si(011)/Si(001) direct silicon bonding (DSB) substrates is a key element of future complementary metal-oxide-semiconductor device technology. In the conventional bonding process, it is necessary to remove interfacial SiO2 to achieve direct atomic bonding. In this study, using X-ray microdiffraction and transmission electron microscopy, we investigate the structural changes caused by oxide out-diffusion annealing (ODA). It is revealed that crystallinity of the bonded Si(011) layer is degraded after low temperature ODA and gradually recovered with an increase in the ODA temperature and annealing time, which is well correlated with the interfacial SiO2/Si morphology. Characteristic domain textures depending on the ODA temperature are also detected.
Authors: Tetsuji Kato, Yuji Ohara, Takaya Ueda, Jun Kikkawa, Yoshiaki Nakamura, Akira Sakai, Osamu Nakatsuka, Masaki Ogawa, Shigeaki Zaima, Eiji Toyoda, Hiromichi Isogai, Takeshi Senda, Kouji Izunome, Hiroo Tajiri, Osamu Sakata, Shigeru Kimura
Abstract: Using X-ray microdiffraction (XRMD) and transmission electron microscopy (TEM) techniques, we have investigated the microscopic structure of Si(011)/Si(001) direct silicon bonding (DSB) substrates. XRMD was performed to measure the local lattice spacing and tilting in the samples before and after oxide out-diffusion annealing. Diffraction analyses for (022) lattice planes with two orthogonal in-plane directions of X-ray incidence revealed anisotropic domain textures in the Si(011) layer. Such anisotropy was also confirmed by TEM in the morphology at the Si(011)/Si(001) bonded interface. The anisotropic crystallinity is discussed on the basis of interfacial defect structures which are proper to the DSB substrate.
Authors: Hideo Kohno, Takafumi Nogami
Abstract: We report a new route to fabricating carbon nanotubes and nanotube interconnects. Insulating Si nanochains covered with hydrocarbon, which are a kind of Si nanowire, can be transformed into distorted nanotubes of carbon by Joule heating. Transmission electron microscopy observations of the transformation reveal that first a surface carbon shell is formed, and then oxide evaporates by Joule heating forming a nanotube.

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