Key Engineering Materials

Preface

Thu, 21 May 2026 00:00:00 +0200

Publication date: 21 May 2026
Source: Key Engineering Materials Vol. 1057

Study of Interface Traps and Scattering Mechanisms in the 4H-SiC MOS Channel Using Gated Hall Measurements

Thu, 21 May 2026 00:00:00 +0200

Publication date: 21 May 2026
Source: Key Engineering Materials Vol. 1057
Author(s): Suman Das, Daniel J. Lichtenwalner, Shane R. Stein, Sei Hyung Ryu
Gated Hall measurements of lateral MOSFET devices can be used to directly measure the inversion layer free carrier density and carrier Hall mobility. From this measurement the total number of charged interface traps (NIT) can be extracted. This provides useful insight into the degree of Coulomb scattering expected. By obtaining gated Hall data from 4° off-axis Si-face (0001) 4H-SiC MOSFETs with varied p-well doping levels, mobility limiting components can also be estimated. For these samples it is observed that interface trapped charge is almost half of the total inversion charge, and thus Coulomb scattering dominates at low Vgs or low transverse (or normal) effective field; while phonon scattering may dominate at moderate effective field, and surface roughness only limits mobility at gate fields higher than the rated usage, or at doping levels much higher than 2×1018 cm-3.

Gate Leakage Imaging of Silicon Carbide Power MOSFETs under Negative-Bias Gate Stress

Thu, 21 May 2026 00:00:00 +0200

Publication date: 21 May 2026
Source: Key Engineering Materials Vol. 1057
Author(s): Andrei Konstantinov, Shagufta Naureen, Sergey Reshanov, Jang Kwon Lim
Visible light emission was observed for negative-bias gate stress of n-channel power MOSFETs in 4H-SiC. The emission intensity is approximately proportional to the current through the gate oxide; and its pattern follows the configuration of active MOSFET channels. We relate the emission to recombination of the electrons injected from the gate into the oxide with valence-band holes from SiC at the surface states at the SiC-to-oxide interface. The gate leakage imaging technique may be helpful for locating different types of gate oxide current crowding, which crowding might cause enhanced wear-out of the gates and early device failure.

Impact of Device Structure on the Performance of Ion-Implanted SiC Phototransistors

Thu, 21 May 2026 00:00:00 +0200

Publication date: 21 May 2026
Source: Key Engineering Materials Vol. 1057
Author(s): Yang Liu, Lei Yuan, Xue Song Liu, Tong Xiao Hou, Bo Peng, Ren Xu Jia, Yu Ming Zhang
The far-UVC band (200–240 nm) is highly attractive for germicidal and solar-blind detection. To address limited surface carrier collection in epitaxial SiC phototransistors, we designed fully ion-implanted lateral phototransistors by combining transistor physics with CMOS-compatible processing. The lateral base width was systematically varied from 1 to 8 μm to investigate its influence on carrier transport and gain. A narrower base significantly enhanced photocurrent amplification, with the 1 μm device reaching 100.7 A/W at 200 nm and 60.0 A/W at 240 nm, while maintaining amplification up to the ~380 nm cutoff. Moreover, dark currents remained as low as 10⁻¹¹ A, confirming the advantage of structural engineering for high-performance far-UVC SiC phototransistors.

1.2 kV SiC MOSFET with Reduced Dynamic Losses Enabled by SiN Gate Dielectric

Thu, 21 May 2026 00:00:00 +0200

Publication date: 21 May 2026
Source: Key Engineering Materials Vol. 1057
Author(s): Tommaso Stecconi, Roger Stark, Paula Reigosa, Nick Schneider, Coris Li, Leon Liang, Lars Knoll
This paper presents a comprehensive electrical evaluation of a 1.2 kV SiC vertical MOSFET incorporating a novel SiN gate dielectric. Compared to a reference device with thermally grown SiO2, the proposed MOSFET achieves superior static performance and lower dynamic losses. Notably, the reduced losses stem from a lower gate–drain capacitance (CGD). Furthermore, the novel MOSFET demonstrates superior thermal and electrical stability of the threshold voltage. All these findings underscore the potential of higher-k dielectrics to simultaneously optimize both static and dynamic performances in SiC power MOSFETs, paving the way for more efficient high-voltage power switches.

Investigation of SiC MOSFETs Gate Capacitance Peak with Biased Drain and Its Relation with Transconductance

Thu, 21 May 2026 00:00:00 +0200

Publication date: 21 May 2026
Source: Key Engineering Materials Vol. 1057
Author(s): Ilaria Matacena, Luca Maresca, Alessandro Borghese, Michele Riccio, Andrea Irace, Giovanni Breglio, Santolo Daliento
SiC MOSFETs still suffer from some open issues, such as the high density of defects existing at the SiC/SiO2 interface. Traps distribution at such interface is complex and it affects the overall performance of the device. Traps influence both current-voltage (I-V) and capacitance-voltage (C-V) characteristics of a SiC MOSFET. In this work, we study the relation of Gate capacitance with biased Drain and transconductance with the aim of investigating the channel properties. The analysis is performed using both experimental setup and numerical framework. Experimental and numerical results both exhibit a sharp capacitance peak in the inversion region at a voltage where transconductance reaches its maximum.

Insight into Bias-Temperature Instability of SiC MOSFETs Using Charge Pumping and Triple-Sense Threshold Measurements

Thu, 21 May 2026 00:00:00 +0200

Publication date: 21 May 2026
Source: Key Engineering Materials Vol. 1057
Author(s): Shane R. Stein, Suman Das, Daniel J. Lichtenwalner, Sei Hyung Ryu
Bias-temperature instability (BTI) is one of the primary sources of parameter drift in silicon and SiC MOSFETs and consequently can determine device lifetime. Most studies of BTI in SiC MOSFETs have characterized the threshold voltage (VT) but not the interface trap density (Nit), leaving uncertainty about the relative contributions of carrier capture and trap creation to the VT shift. In this study, to lend insight into the physical mechanisms responsible for BTI in SiC MOSFETs, we measure Nit during positive bias-temperature stress (BTS) using the charge pumping (CP) technique. We also characterize the shift in VT and hysteresis using the triple-sense method [1], [2] for comparison with the Nit changes to evaluate whether the changes in Nit are responsible for the VT and/or hysteresis changes, and demonstrate the utility of the technique for reliable characterization of VT and hysteresis in SiC MOSFETs.

Experimental Analysis of 4H-SiC CMOS NOT Logic Gate Down to 100K

Thu, 21 May 2026 00:00:00 +0200

Publication date: 21 May 2026
Source: Key Engineering Materials Vol. 1057
Author(s): Luigi di Benedetto, Nicola Rinaldi, Mathias Rommel, Alexander May, Leander Baier, Rosalba Liguori, Alfredo Rubino, Gian Domenico Licciardo
In this paper, the electrical characterizations of a 4H-SiC CMOS NOT logic gate are performed in the temperature range from 300K down to 100K and the results are analyzed. The integrated circuit is fabricated with the Fraunhofer IISB 4H-SiC 2μm CMOS technology and the lateral NMOSFET and PMOSFET have channel form factor of 6/6 and 44/6, respectively. The circuit is supplied with a 20V. The curves show a reduction of the threshold voltage from 8.96V to 6.85V reducing the temperature from 300K to 100K and an ever-widening region in the High side (NMOSFET in saturation and PMOSFET in triode regime) compared to the Low side (NMOSFET in triode and PMOSFET in saturation regime). However, the noise margins are still wide enough for practical applications, making the circuit still useful. The behavior can be ascribed to a reduction of the conductivity of the PMOSFET with the decreasing of the temperature. Finally, analysis also focuses on the power dissipation during the transition of the output voltage from high (low) to low (high).

Characterization of 4H-SiC Lateral MOSFETs up to 773 K

Thu, 21 May 2026 00:00:00 +0200

Publication date: 21 May 2026
Source: Key Engineering Materials Vol. 1057
Author(s): Nicola Rinaldi, Luigi di Benedetto, Mathias Rommel, Alexander May, Leander Baier, Rosalba Liguori, Alfredo Rubino, Gian Domenico Licciardo
Experimental analysis of 4H-SiC lateral MOSFETs characteristics up to 773K is shown. The reduction of threshold voltage, VTH, and the increase of the field effect channel mobility, µCH, with temperature cause an increase of MOSFET current up to 623K. However, when scattering with lattice vibration starts to be predominant, µCH decreases with an abrupt drop at 773K, reducing MOSFET current. Channel resistance, RCH, decreases with the temperature up to the range between 523 K and 573 K, implying possible thermal instability effects. However, when the temperature increases over this range, the thermal scattering predominates and RCH again increases, ensuring thermal stability of MOSFETs.

Application of a New Method and Criterion for Analyzing Repetitive Surge Current in Commercial SiC Schottky Diodes

Thu, 21 May 2026 00:00:00 +0200

Publication date: 21 May 2026
Source: Key Engineering Materials Vol. 1057
Author(s): Jenny Damcevska, Sima Dimitrijev, Daniel Haasmann, Philip Tanner, Fan Peng Zeng, Lan Luo, Ying Xin Cui, Yu Zhong, Ji Sheng Han
The repetitive peak forward surge current (IF,RM) is a practically important parameter for SiC Schottky diodes, as it ensures reliable and robust circuit designs. However, there is no established method and criterion for this imperative parameter. Manufacturers predominantly provide the non-repetitive peak forward surge current value (IF,SM) in datasheets, which is generally determined from derated measured peak currents that cause diode failures. Consequently, it is assumed that IF,SM enables diodes from various manufacturers with different structural designs to be compared in terms of their repetitive surge current performance. In this paper, we will demonstrate the need for a consistent criterion and a method to determine IF,RM by analyzing repetitive surge currents in representative commercially available SiC Schottky diodes. The analysis is based on a recently proposed method and criterion for the repetitive peak surge current in SiC Schottky diodes that ensures the junction temperature does not exceed the maximum device rating, which is 175°C for the commercially available devices analysed in this study.

Short-Circuit Reliability Analysis of SG-MOSFETs vs Planar 4H-SiC MOSFETs

Thu, 21 May 2026 00:00:00 +0200

Publication date: 21 May 2026
Source: Key Engineering Materials Vol. 1057
Author(s): Pei Chun Liao, Kung Yen Lee, Ruei Ci Wu, Yan Yu Wen, Po Yu Cheng, Wei Xiang Wang
This work investigates the short-circuit (SC) reliability of Split-Gate (SG) versus planar 4H-SiC MOSFETs through TCAD simulations. While SG-MOSFETs effectively reduce gate-drain capacitance and improve switching performance, SG-MOSFETs exhibit enhanced short-circuit failure effects. Structural optimization—such as thicker drift regions, extended gate lengths, and narrowed JFET widths—can improve SC withstand time (SCWT). However, SG-MOSFETs suffer from intensified electric field crowding and enhanced drain-induced barrier lowering (DIBL), leading to greater post-SC leakage and thermal instability. Results suggest SG-MOSFETs require careful field and oxide engineering to ensure reliability under fault conditions.

Impact of Active Cell Geometry on the Static Performance of 10-kV 4H-SiC JBS (Junction Barrier Schottky) Diodes

Thu, 21 May 2026 00:00:00 +0200

Publication date: 21 May 2026
Source: Key Engineering Materials Vol. 1057
Author(s): Hojung Lee, Justin Lynch, Stephen A. Mancini, Skylar deBoer, Miguel Hinojosa, Aivars Lelis, Woongje Sung
This study investigates the influence of active cell geometry on the static performance of 10-kV 4H-Silicon Carbide (SiC) Junction Barrier Schottky (JBS) diodes. Two types of diodes were fabricated and characterized, one with a hexagonal cell and the other with a stripe cell. While forward conduction characteristics were comparable, the reverse leakage current of the hexagonal cell was more than two orders of magnitude lower than that of the stripe cell at 8 kV. 3D TCAD simulations revealed that this discrepancy stems from strong electric field concentrations both at the bottom corners of the P+ junctions and at the center of the Schottky contact in the stripe structure. These localized fields reduce the Schottky barrier height and enhance electron injection. In contrast, the hexagonal cell exhibited a more uniform electric field distribution in both regions, effectively suppressing leakage current. These findings underscore the critical role of active cell geometry in achieving robust reverse blocking performance in ultra-high-voltage SiC JBS diodes by clarifying the physical mechanisms contributing to leakage current behavior.

Fowler-Nordheim Current at Negative Gate Bias in SiC MOSFETs

Thu, 21 May 2026 00:00:00 +0200

Publication date: 21 May 2026
Source: Key Engineering Materials Vol. 1057
Author(s): Dick Scholten, Johannes Ziegler, Wolfgang Feiler
We show that various commercially available silicon carbide MOSFETs exhibit significant gate leakage current at gate voltages below 20 V. With prolonged negative bias stress, this leakage current reduces by several orders of magnitude. Literature [1–3] suggests that this current is due to hole current from the silicon carbide and explain the current reduction by the discharge of electrons at the SiC/SiO2-interface. However, measurements on n⁺-doped SiC-MOSCAPs, where we avoid hole current, exhibit similar gate leakage behavior, indicating that there might be an alternative explanation. Further measurements show that the threshold voltage is not significantly impacted by the negative gate bias stress, indicating that the channel region is not involved in the gate leakage current. Devices with a floating source do not show leakage, and we therefore conclude that the gate leakage is located in the source region. An analytical calculation is used to show that field enhancement at the edges of the polysilicon gate electrode, assuming a corner radius below 10 nm, may explain the onset voltage of the gate leakage current at negative bias. Alternatively, gate oxide damage from the polysilicon etching process, may also explain the leakage current. The reduction of the onset voltage of the gate leakage with prolonged negative voltage gate stress, may be explained by significant electron trapping due to the high local current density at the poly-silicon gate electrode corner.

Body Diode Reliability and Reverse Recovery Characteristics of Short Tapered SJ-MOSFET Fabricated by MeV Al Ion Implantation

Thu, 21 May 2026 00:00:00 +0200

Publication date: 21 May 2026
Source: Key Engineering Materials Vol. 1057
Author(s): Takeshi Tawara, Kensuke Takenaka, Syunki Narita, Shinsuke Harada
MeV-SJ-MOSFET with short tapered SJ columns was developed by high-energy (MeV) Al ion implantation and was evaluated for the reverse recovery characteristics and the body diode reliability compared to those of Multiepi-SJ. MeV-SJ alleviated the increase in on-resistance at elevated temperatures regardless of short SJ columns and exhibited soft reverse recovery characteristics due to the short tapered SJ shape. MeV-SJ also suppressed the body diode degradation more than Multiepi-SJ. It was considered that the carrier lifetime of drift layer of MeV-SJ may be decreased by non-radiative defects.

Optical Critical Dimension Metrology for the SiC Trench MOSFET Process

Thu, 21 May 2026 00:00:00 +0200

Publication date: 21 May 2026
Source: Key Engineering Materials Vol. 1057
Author(s): Boglárka Dikó, Oleg Rusch, Julien Körfer, Zsófia Kiss, Attila Sütő, Emeric Balogh
Silicon carbide (SiC) MOSFETs are widely utilized in power device applications for their numerous advantages, and the device’s properties can be further optimized through the implementation of trench structures. The formation of the trench structure is a multi-step process, in which it is important to monitor the result of each step and ensure that the structure meets the desired requirements. OCD (optical critical dimension) metrology can provide a fast, non-destructive solution for this purpose. In this article, an OCD analysis of structures at two different process steps is presented and compared with the results from the electron microscopy images. OCD results show high sensitivity to the geometrical dimensions of the structure and produce a good correlation with the electron microscopy images. This metrology can provide a means to detect subtle structural differences without causing any damage to the sample.

Body Diode Performance of the 4H-SiC 3.3 kV Semi-SJ MOSFET

Thu, 21 May 2026 00:00:00 +0200

Publication date: 21 May 2026
Source: Key Engineering Materials Vol. 1057
Author(s): Kyrylo Melnyk, Arne Benjamin Renz, Mustafa Akif Yildirim, Nikolaos Iosifidis, Qin Ze Cao, Jose Ortiz-Gonzalez, Vishal A. Shah, James A. Gott, Peter Michael Gammon, Marina Antoniou
This study investigates static and dynamic behavior of a 3.3 kV semi-Superjunction (SJ) MOSFET, compared with a conventional planar MOSFET. The semi-SJ was designed using a cost-effective trench side-wall implantation and SiO2 refill fabrication method and evaluated through TCAD simulations. The optimized semi-SJ MOSFET designs, reduces RON by 19% and increases BV by 500 V compared with the planar MOSFET, while maintaining a comparable reverse recovery charge (QRR). The proposed semi-SJ design demonstrated the best RON×QRR figure of merit (17.8 mΩ·µC), outperforming the conventional planar MOSFET design (19.7 mΩ·µC).

An Improved Analytical Model for SiC P-I-N Diode Reverse Recovery

Thu, 21 May 2026 00:00:00 +0200

Publication date: 21 May 2026
Source: Key Engineering Materials Vol. 1057
Author(s): Giorgian Borca-Tasciuc, T. Paul Chow
We generalize a recent Si P-i-N reverse-recovery (RR) model to more accurately capture 4H-SiC diode behavior by adding deep-acceptor-limited anode injection, strong recombination (due to >100x shorter optimized high-level lifetimes compared to Si), and improved modeling of the depletion layer dynamics. Closed-form expressions for the growth of the depletion layer are derived, enabling analytical estimates for QRR, tRR, and JPR. The model is validated against Sentaurus RR simulations of optimized 4H-SiC P-i-N diodes spanning BV = 6–17kV and di/dt = 10 A/µs–10 kA/µs, achieving an average reduction in error of >90% for estimations of key switching performance parameters (QRR, tRR, JPR). By correctly capturing the dependence of QRR on di/dt, the model enables better estimates for the high-level lifetime (τHL) directly from the RR waveforms. The differential form enables straightforward utilization of the model to analyze non-idealized RR waveforms. Overall, the generalized model reveals a more favorable QRR–VF trade-off than implied by the unmodified Si model and improves first-order device optimization prior to full design.

Anomalous Reverse Recovery of Body Diode in 4H-SiC Superjunction DMOSFET

Thu, 21 May 2026 00:00:00 +0200

Publication date: 21 May 2026
Source: Key Engineering Materials Vol. 1057
Author(s): Giorgian Borca-Tasciuc, Reza Ghandi, Collin W. Hitchcock, Tat Sing Paul Chow
We report an anomalous reverse-recovery (RR) of the body diode in a 3.3 kV 4H-SiC superjunction (SJ) DMOSFET: at 77 K, QRR,sp increases by 1.4×–3.5× versus room temperature and 5× versus 195 K, and JPR increases by >2×, while tRR changes by only <30ns. A clear dependence of QRR,sp on the ramp rate at 77K indicates the QRR,sp is not due to additional depletion charge. Current-controlled negative resistance (CCNR) is also observed solely for the SJ body diode at 77K. The voltage waveforms strongly suggest the additional QRR,sp is due to dynamic breakdown of the SJ due to transient charge imbalance of the pillars caused by delayed hole emissions of the deep acceptors. The anomalous behavior is qualitatively reproduced in simulation. We also benchmark a 3.3kV Charge Balance (CB) 4H-SiC DMOSFET along with the SJ device from 77–423 K using an inductive double-pulse test. For T > 77 K the switching for both devices is dominated by the depletion capacitance (weak QRR,sp dependence on the ramp rate): the SJ device turns off faster (tRR = 0.3–0.8× CB), is snappier (tB/tA = 0.23–0.56× CB), and shows larger JPR (1.8–2.8× CB) while recovering less charge (QRR,sp = 0.4–0.8× CB). The CB device shows the expected increase of QRR,sp with temperature and only modest tRR temperature variation. Overall, the CB device provides softer, predictable RR without a cryogenic anomaly, whereas SJ delivers the shortest tRR above 77 K but exhibits the 77 K anomalous increase and is consistently snappier.

Dynamic Conduction Behavior of SiC-MOSFETs in the Sub-Threshold Regime and the Impact of Deep Oxide Traps to the Channel Depletion

Thu, 21 May 2026 00:00:00 +0200

Publication date: 21 May 2026
Source: Key Engineering Materials Vol. 1057
Author(s): Marvin Gloth, Drinas Kelmendi, Hamed Azimi, Benjamin Weigt, Tobias Erlbacher
This paper investigates the dynamic conduction behavior of silicon carbide (SiC) MOSFETs in thesub-threshold regime. We demonstrate that controlled gate bias preconditioning, combined with timeresolvedelectrical measurements in thermal equilibrium, reveals a notable drift in the source-drainvoltage Vsd. The direction of this drift depends on the polarity of gate preconditioning and is directlyrelated to variations in the channel conduction. These effects are shown to be attributed to chargerelease from deep oxide traps, leading to a gradual shift in the flat-band voltage (Vfb) over time.Experimental results reveal that these dynamic effects are most prominent in the depletion and weakinversion regimes. Our findings highlight the influence of oxide trap dynamics on the body diodeforward voltage (Vf) and its significance for the reliability of SiC devices, specifically in its role asthe temperature-sensitive parameter.

Influence of Cell Structure and Topology on Coss of 4H-SiC MOSFET

Thu, 21 May 2026 00:00:00 +0200

Publication date: 21 May 2026
Source: Key Engineering Materials Vol. 1057
Author(s): Ruei Ci Wu, Kung Yen Lee, Pei Chi Liao, Pei Chun Liao, Jui Chi Chu
This study demonstrates that the output capacitance (Coss) of a 4H-SiC MOSFET is proportional to the length of JFET (LJFET) at a low Vds, since under this condition, the gate-to-drain capacitance (Cgd) may account for nearly half of Coss. Furthermore, when Vds is low, the Coss of MOSFETs with square and hexagonal cell topologies is approximately 20% and 25% higher than that of MOSFETs with the strip cell topology, respectively, due to larger JFET areas. However, when Vds is higher, the Coss of MOSFETs with square and hexagonal cell topologies is lower because of the lower drain-to-source capacitance (Cds) resulting from smaller Pwell areas. The split-gate MOSFET can reduce Cgd, but the smaller poly-gate area decreases the depletion capability, resulting in a higher Cds. As LJFET of the MOSFET decreases, Cgd becomes lower, which may shorten the switching time, but due to the increased length of Pwell (LPW), the reverse recovery current (Irr) increases. This study proposes partially increasing the gate oxide thickness. Although this may slightly increase Cds, the shorter switching time results in a 5% reduction in the turn-on switching loss (Eon).