Wide-Range Prediction of Ultra-High Voltage SiC IGBT Static Performance Using Calibrated TCAD Model

In this paper, a technology computer-aided design (TCAD) model of a silicon carbide (SiC) insulated-gate bipolar transistor (IGBT) has been calibrated against previously reported experimental data. The calibrated TCAD model has been used to predict the static performance of theoretical SiC IGBTs with ultra-high blocking voltage capabilities in the range of 20-50 kV. The simulation results of transfer characteristics, IC-VGE, forward characteristics, IC-VCE, and blocking voltage characteristics are studied. The threshold voltage is approximately 5 V, and the forward voltage drop is ranging from VF = 4.2-10.0 V at IC = 20 A, using a charge carrier lifetime of τA = 20 μs. Furthermore, the forward voltage drop impact for different process dependent parameters (i.e., carrier lifetimes, mobility/scattering and trap related defects) and junction temperature are investigated in a parametric sensitivity analysis. The wide-range simulation results may be used as an input to facilitate high power converter design and evaluation. In this case, the TCAD simulated static characteristics of SiC IGBTs is compared to silicon (Si) IGBTs in a modular multilevel converter in a general high-power application. The results indicate several benefits and lower conduction energy losses using ultra-high voltage SiC IGBTs compared to Si IGBTs.


Introduction
Traditionally in high power electronic applications, silicon (Si) based bipolar charge carrier transistors (i.e., insulated-gate bipolar transistors (IGBTs) and Thyristors) have been the main choice of semiconductor switches due to low conduction losses, high blocking voltage capability and robustness. As commercial SiC-based power semiconductor devices have begun to enter the low/medium power market in various applications [1], the devices for high power applications are predicted to enter the market when several manufacturing and packaging challenges have been resolved/improved (i.e., high quality SiC substrates, epitaxial growth, contacts and low material defect densities). It is predicted that systems using these high blocking voltage devices may offer system level benefits such as reduced number of submodule cells/devices, less complex system and reduced cooling requirement and station foot-print [2]. For initial converter comparison/evaluation, it is important to perform wide-range theoretical evaluations of high voltage SiC devices to predict the possible impact of these devices in high power applications.
In the research literature, high voltage SiC IGBTs have been experimentally demonstrated up to 27 kV [3] and numerical simulation studies have investigated the SiC IGBT characteristics in the range of 15-25 kV [4] and empirical/analytical calculation results up to 50 kV [5]. Kimoto et al. [6] stated that the forward voltage drop significantly increases for SiC devices with blocking voltage capabilities beyond 50-60 kV, due to band-to-band recombination. Today, no experimental results or finite-element simulation results for ultra-high voltage (25-50 kV) SiC IGBTs are visible in the literature. Therefore, the SiC IGBT characteristics in this blocking voltage range needs thorough investigation to clarify the potential in different applications and justify/promote further research in this field, which is filled with several manufacturing and packaging challenges. For accurate device design and its electrical behavior predictability, a wide-range numerical simulation approach is required since several of the process dependent parameters (i.e., carrier lifetimes, mobility and trap related defects) of the manufacturing process are still uncertain at this point. A sensitivity analysis of such parameters is a suitable method to investigate future device performance.

TCAD Model Description
A general 4H-SiC IGBT punch-through structure is implemented in the Synopsys Sentaurus TCAD simulation platform according to Fig. 1. The implemented IGBT structure is based on the design of a 22 kV IGBT [7,8] (i.e., drift region thickness (doping) = 180 μm (ND = 2×10 14 cm -3 ), gate oxide thickness = 500 Å, channel length (doping) = 1 μm (NCH = 5×10 17 cm -3 ), JFET width = 5 μm, cell pitch = 9.5 μm, buffer layer thickness = 2 μm and area scale factor = 3.9×10 6 ) and is used for calibration of the TCAD model against experimental data [7,8]. A realistic SiC/SiO2 trap profile [9] with increasing trap concentrations at the edges is adapted, which strongly effects the channel mobility due to scattering mechanisms at the interface (i.e., acoustic, surface roughness, coulomb scattering). Furthermore, as the SiC epitaxial growth process is still under evolvement for high voltage devices, the 4H-SiC material contains various levels of deep-level traps and crystal dislocations which limits the charge carrier mobility and lifetime. The epitaxial growth conditions define the defect type, their concentration and their physical location. As-grown n-doped SiC epitaxial-layers may attain trap concentrations in the range of 10 12 -10 15 cm -3 depending on growth conditions [10,11]. To obtain a longer charge carrier lifetime, especially for high voltage bipolar devices, defect densities must be decreased to the order of 1×10 12 cm -3 or even lower [12]. For the as-grown epitaxial layer, the measured lifetime of 1.1 μs was obtained and was greatly improved to 26 μs after the defect reduction process in the 220 μm thick epitaxial layer. Generally speaking, thicker epitaxy is more likely to have higher defect densities and thus less likely to reach ideal bulk mobility values due to impurity scattering. Therefore, these process dependent parameters are kept as model parameters and the model was calibrated by using a design of experiment (DOE) approach. Furthermore, previously calibrated 4H-SiC material related parameters were incorporated in the model [13]. The temperature dependent impact ionization coefficients derived by Zhao et al. [14] and anisotropic coefficients by Hatakeyama et al. [15] are used for breakdown voltage simulations. The incorporated physical models are summarized in Table 1.

4H-SiC IGBT Simulation Results
Model Calibration. The TCAD IGBT simulation results indicate satisfactory correlation with experimental data provided from [7,8], using a set of process dependent parameters extracted from the DOE process (i.e., SiC/SiO2 DIT = 2. Breakdown Voltage. The breakdown voltage characteristics of the four theoretical devices (20-50 kV) are simulated with the calibrated device structure using the same physical models and parameters but with modifications stated in Table 2. For simplicity, only the active part of the device is simulated, and no junction termination edge is included. The charge-carrier lifetime-dependent breakdown voltage characteristics are presented in Fig. 2b, where τA,LOW = 1 μs and τA,HIGH = 100 μs, assuming the typical ratio of τE/τH = 5. As the charge carrier lifetime increases, the thermally generated carriers survive for a longer time and hence more active carriers are available for conduction in the drift region, which increases the leakage current. Similarly, the enhanced number of active carriers reduce the critical point of avalanche multiplication to a lower voltage level, resulting in a lower breakdown voltage capability of the devices. blocking voltage due a to thicker, more resistive drift region of the device, as expected. Using traditional Si packaging technologies (e.g., 300 W/cm 2 ), the on-state current (density) handling capability ranging from 27-55 A/cm 2 and future SiC packaging technologies (e.g., 500 W/cm 2 ) [17] results in 39-78 A/cm 2 for the four theoretical devices. Parametric Sensitivity Analysis. The 4H-SiC manufacturing technologies are continuously evolving and reduction of defects and traps will improve the process dependent parameters. Therefore, a wide-range parametric sensitivity analysis is performed to study the impact on VF for process dependent parameters and temperature. These results are presented in Fig. 4. The forward voltage drop decreases with increasing charge carrier lifetime, due to that more carriers in the drift region enables higher level of conductivity modulation. For low carrier lifetimes, the impact of mobility increases with blocking voltage capability. With higher carrier lifetimes, the impact of mobility is not as large and reasonable conductivity modulation is yet achieved. Material quality has a significant impact on the device characteristics and high-quality SiC material is crucial for high voltage devices. The forward voltage drop increases with temperature since bulk mobility reduces with temperature, even though more excess charge carriers are available in the drift region. Furthermore, simulations indicate that the SiC/SiO 2 interface trap density has a minor impact on the forward voltage drop (i.e., DIT = 2.1×10 13 cm -2 eV -1 vs. DIT = 2.1×10 12 cm -2 eV -1 corresponds approximately to ΔVF ~ 0.1 V for all four devices in the investigated charge carrier lifetime range). Depending on the gate process conditions, experimental DIT concentrations for SiC devices in the range of 3×10 11 -2×10 14 cm -2 eV -1 have been obtained [9,18]. Fig. 4. Impact on SiC IGBT forward voltage drop for different charge-carrier lifetimes and a) mobility (i.e., µE/H_Normal = 950/125 cm 2 /Vs vs. µE/H_Reduced = 700/60 cm 2 /Vs at T = 300 K) and b) temperature (i.e., T = 300 K vs. T = 448 K with µE/H_Reduced = 700/60 cm 2 /Vs).

Comparison of Conduction Losses for Si IGBTs and 4H-SiC IGBTs
The simulation output is used for initial evaluation and comparison between ultra-high voltage SiC IGBTs and Si-based device structures in high power applications. A Modular Multilevel Converter (MMC) for a high-power application serves as a test case (e.g., system voltage VDC = 640 kV, modulation index (M) = 1, rated power S = 1 GW). The modularity of such converters enables a good scalability. The converter cell or power electronic building blocks (PEBB) can be designed with arbitrary voltages. A PEBB with a nominal voltage of 16.8 kV employing 30 kV SiC IGBTs should therefore be compared to a solution with the same voltage rating but using series connected Si IGBTs, or a series connection of PEBBs using a single Si IGBT. Note that both Si BIGT configurations yield the same result, since only the conduction losses are considered here. As an example, a TCAD simulated 30 kV SiC IGBT with antiparallel SiC PiN diode [19] is compared to a state-of-the-art 4.5 kV Si Bi-mode Insulated Gate Transistor (BIGT) [20]. The active area of the employed power semiconductor is kept constant. In a second comparison, it is accounted for a lower active area in the ultra-high voltage SiC devices due to a bigger junction termination edge (JTE) area. The converter test case parameters and semiconductor device parameters are summarized in Table 3.  Fig 5a, where the voltage drop is normalized by the rated blocking voltage. Two cases are presented, the first case with equal active area (AA = ATOT) and the second case with equal total area including the required JTE for each device (AA = ATOT-AJTE). In both cases, the ultra-high voltage SiC device indicates lower normalized voltage drop than Si BIGT counterparts.
Furthermore, the normalized semiconductor conduction losses of the high-power converter conducting active power employing Si BIGTs or SiC IGBTs are visualized in Fig. 5b. Note that the device area for both technologies is scaled to fit the RMS current appearing in the converter. The comparison indicates that the TCAD simulated 30 kV SiC IGBTs are conduction loss competitive with a series connection of state-of-the-art Si BIGT devices; even with a reduced active area due to larger JTE, where a conduction loss reduction of approximately 30 % can be achieved. Together with a reduction of system complexity, control hardware, cables, and fibers (due to a lower amount of PEBBs), this presents a promising alternative to existing high-power converters with high-voltage Si devices. Fig. 5. a) Comparison of conduction capability normalized by blocking voltage with data from 30 kV SiC IGBT TCAD simulation and [20] for equal active area (AA,Si = AA,SiC = ATOT = 1 cm 2 ), and equal total area including JTE (AA = ATOT-AJTE, AA,Si = 0.706 cm 2 , AA,SiC = 0.49 cm 2 ). b) Conduction loss comparison between Si BIGT and TCAD simulated SiC IGBT in a general high-power system. The losses are normalized to the Si BIGT implementation.

Summary
A 4H-SiC IGBT TCAD model has been calibrated against experimental data and has been used to widely investigate static performance of high voltage SiC IGBTs (20-50 kV). The impact of various process dependent parameters and temperature has been studied. A comparison of conduction energy losses between SiC and Si based converter cells has been evaluated for their potential use in highpower application systems. The calculation indicates that a conduction loss energy reduction of 30 % may be achieved by using 30 kV SiC IGBTs. Furthermore, the wide range simulation data may serve as input to future converter evaluation studies in various high-power applications.