Vanadium Incorporation in 3C-SiC Epilayers and its Consequences for Electrical Properties of 3C-SiC Material

The present experimental study demonstrates the feasibility of Vanadium doping of 3CSiC hetero-epitaxial material. Some of Vanadium incorporation trends as well as the influence of Vanadium doping on 3C-SiC resistivity are observed.


Introduction
Semi-insulating (SI) Silicon Carbide is used at industrial scale as substrate material for high frequency GaN based devices in order to minimize the parasitic conduction that reduces the device performance. During last 10 years it became also the support of choice for graphene related devices. Highly resistive SiC substrates were obtained through the introduction of Vanadium (V) doping in PVT bulk growth in mid-90's. However, the V concentration close to solubility limit, necessary to compensate important residual doping of the crystal, was at the origin of degradation of structural quality of bulk material. Progressively, V-doped SiC substrates were replaced by high purity semiinsulating material using intrinsic defects (ex C-vacancies) to compensate the residual doping.
A renewed interest in Vanadium doping came in late 2010's with the possibility of introducing V in epitaxially grown 4H-SiC. Strongly resistive epilayers of well controlled thickness and resistivity were obtained within (relatively) cheap CVD growth process [1,2].
In the case of cubic silicon carbide (3C-SiC), one of the issues that prevent the development of electronic devices based on heteroepitaxial 3C-SiC epilayers is the presence of important leakage current related to existence of intrinsic structural defects within the material (stacking faults, µ-twins, grain boundaries) [3,4], especially in the near interface region of the epilayer. One could expect that the incorporation of Vanadium, especially during the first phase of the growth, should reduce the leakage and improve the electrical properties of the material.
In the present contribution we test the feasibility of Vanadium doping of 3C-SiC epilayers grown on silicon, investigate some of incorporation trends and evaluate the influence of Vanadium incorporation on electrical properties of 3C-SiC material.
SiC(100) epilayers were grown with various VCl4 flowrates to establish the maximum Vanadium supply that does not deteriorate the structural / morphological properties of 3C-SiC. In second series, multilayer 3C-SiC(100) and (111) samples with variable Vanadium supply were prepared for SIMS analyses. Finally, a series of thin (< 0.6 µm) 3C-SiC epilayers was grown on highly resistive Si(111) substrates (ρ > 5 kΩcm). Contactless sheet resistance measurements were performed on these epiwafers after backside polishing (necessary to remove the parasitic conductive poly-3C-SiC deposited on the backside).

Experimental Results and Discussion
Vanadium incorporation in 3C-SiC. Figure 1 shows typical optical microscopy images of 4 µm thick 3C-SiC(100) epilayers. Films with VCl4 flowrates up to 1.8×10 -2 sccm present the same morphology as for standard, undoped (NID) film. For higher Vanadium supply (starting from 3.6×10 -2 sccm), surface defects appear.   Figure 2 shows the depth profile of Vanadium incorporation [V] measured by SIMS in 3C-SiC(100) film grown under VCl4 supply increasing step by step. SIMS analyses were precisely calibrated using reference sample with controlled Vanadium concentration. To avoid the structural deterioration of the sample we limited the Vanadium supply to 1.8×10 -2 sccm. Sublayers are clearly defined and the interface between strongly V doped and the topmost, V-free, sublayer is sharp ([V] drop > 4 decades). Minor Vanadium memory effect persists however, as reflected by presence of small [V] peak at 3C-SiC/Si interface.    We compare in Figure 5 the influence of C/Si ratio on [V] in 4H-SiC Si-face and 3C-SiC(100) under same VCl4 supply ΦVCl4=5.4×10 -3 sccm. In 4H-SiC, [V] slightly increases with increasing C/Si ratio, suggesting preferential incorporation on Si sites, which is expected taking into account atomic radii. In 3C-SiC this increase is marginal (but the study could be performed only for C/Si>1.5). Together with almost identical incorporation in (100) and (111) oriented samples (Fig. 3), the results obtained in 3C-SiC do not confirm that Vanadium incorporates on Si-sites.
Electric properties of 3C-SiC:V. The conditions of Vanadium supply during the growth of a series of thin, highly resistive 3C-SiC/Si(111) templates are reported in Table I. Eddy current sheet resistance of standard, Vanadium-free reference sample (A) is 2 kΩ/sq (mean value of 17 points cartography on 100mm diameter wafer). The resistance of sample (B), with V-doping in topmost part of epilayer increases to 9 kΩ/sq. In Sample (C), where the Vanadium was supplied during entire CVD step, further increase to 14 kΩ/sq was recorded. Introduction of VCl4 during carbonization step does not seem to further enhance the epilayer sheet resistance (sample D). Finally, for thicker epilayer with increased V supply we recorded 15 kΩ/sq. This enhancement of sheet resistance with respect to Vanadium free epilayer is certainly due to Vanadium doping. However, taking into account the reduced 3C-SiC thickness (0.4-0.6µm), corresponding 3C-SiC resistivity remains below 1 Ωcm, very far from the values of bulk SI 4H-SiC material (typically >10 10 Ωcm).
I-V measurements were performed using Hg probe in vertical configuration (Hg contact, φ ~ 0.8 mm, on the topside of the wafer, mechanical metal contact, φ ~ 25 mm, on the backside) for different types of SiC material. The DC I-V curves (in ±40 V range) are reported in Figure 6. Obviously, this approach does not allow us to statue quantitatively on the resistivity of SiC material. However, a qualitative differences can be clearly seen: for highly conductive 4H-SiC:N+ substrate (ρ ~ 0.02 Ωcm), 1 A current range is reached for voltages below ±10 V. After the deposition of 20 µm thick 4H-SiC:V epilayer ([V] ~ 4×10 15 at/cm 3 ) on such conductive substrate, the I-V vertical characteristics become similar to those of insulating glass (measured current below 10 -9 A).
For 3C-SiC/Si the I-V curves are reported for 3 samples with differently doped 3C-SiC epilayer: NID, [N] > 10 19 cm -3 , [V] ~ 10 19 cm -3 , grown on lowly conductive substrate (ρ > 200 Ωcm). All the samples exhibit similar electric behavior indicating that vertical conduction is dominated by the substrate resistivity. The Vanadium related increase of 3C-SiC resistivity is too small to reduce significantly the vertical conductance of the epiwafer. We may conjecture that despite high Vanadium concentration, not all V atoms are acting as traps or that conduction through extended defects paths in 3C-SiC cannot be screened by the presence of V atoms. Even if at this stage we did not observe by optical microscopy any big precipitation defects reported in [1], we can't exclude the formation of submicron, V-rich clusters. The study will be continued to verify this hypothesis.

Conclusion
Through this study we demonstrated the feasibility of V doping of CVD grown 3C-SiC epilayers and validated the V-related increase of 3C-SiC resistivity. The effect of Vanadium introduction is not as spectacular as in 4H-SiC epilayers, where semi-insulating character of epilayer was achieved. However, observed increase of epilayer resistivity may still be useful ex. in preparation of templates for III-N based RF HEMT devices.