Sensitivity of Dit Extraction at the SiO2/SiC Interface Using Quasi-Static Capacitance-Voltage Measurements

In this work, we compare different quasi-static capacitance-voltage measurement systems by analyzing 4H-SiC n-type MOS capacitors and studying the influence of systematic errors when extracting the interface trap density (Dit). We show that the extracted Dit strongly depends on the calculation of the surface potential due to variations of the integration constant. In addition, the ramp-rate during the quasi-static measurement is identified as a sensitive measurement parameter whose noise level is amplified in the Dit extraction.


Introduction
Owing to its beneficial electrical and thermal properties, silicon carbide (SiC) is a well-established material for power electronic devices. However, the widespread use of SiC MOSFETs in power applications results in increasingly demanding requirements regarding their performance and reliability. Despite the commercial success of SiC MOSFETs, there are still unsolved reliability issues related to the number of defects and near-interface traps situated at the interface between silicon carbide and silicon dioxide (SiO2) that are generated during thermal oxidation [1]. Therefore, a careful analysis of the density of interface traps (Dit) and their effect on the device performance is crucial for process development and monitoring.
Different methods have been used to study the Dit at the SiO2/SiC interface [2], among which capacitance-voltage (CV) measurements are the most established technique due to their apparent simplicity in both execution and interpretation of results. The Dit can be extracted as a function of the energy position in the bandgap by comparing a low-frequency or quasi-static capacitance curve with a high-frequency measurement [3] or a theoretical CV curve [4].
However, in quasi-static capacitance measurements, the values obtained for low capacitances are very sensitive to the setup parameters used in the analysis of Dit. This can lead to inaccuracies that are difficult to detect but strongly influence the final result. Here we present a study of the systematic errors encountered when performing quasi-static capacitance-voltage measurements and the subsequent extraction of Dit for the analysis of the SiO2/SiC interface.

Experimental Details
The devices tested are 4H-SiC n-type MOS capacitors. For the results in Fig. 1, the analyzed MOS capacitors have a doping concentration of ND = 4.7x10 15 cm -3 and 48 nm of thermal oxide grown at 1300 °C. The high-frequency capacitance was measured using the Keithley 4200A-SCS.
The quasi-static measurements shown in Fig. 2

Extraction of Surface Potential
For the study of the Dit, we use the C-ψs method [4]. In this method, the relationship between the applied gate bias (Vg) and the surface potential ( ) is calculated with the quasi-static (CQS) and oxide capacitance (Cox) by solving the Berglund integral [5]: where: Following the C-ψs method [4], the constant is determined from the extrapolation of a linear fit of ′ vs 1/ 2 , where the depletion capacitance (Cdep) is obtained from a high-frequency CV measurement, i.e. assuming there is no influence from traps. Here we observe that the ′ range used to perform the linear fitting influences the value of . Even though the shift in seems small, it can have a strong impact on the Dit along the energy axis [6], causing a wrong evaluation of the defect density at the SiO2/SiC interface. In order to extract , it is crucial to limit the linear fit to the range where the MOS capacitor is in depletion, i.e. were ′ decays linearly with 1/ 2 , and to not include the voltage range of deep depletion, where the relation ′ vs. 1/ 2 is not linear anymore. The depletion region boundaries can be identified by considering that the slope of 1/ 2 is inversely proportional to the doping concentration of the epitaxial layer [3]. In Fig. 1a, the results of the CV analysis are shown, where the blue curve was obtained at a measurement frequency of 2 MHz. The red and orange curves are obtained by fitting in a ′ range that leads the MOS capacitor into deep depletion and depletion. The dark green curve is evaluated using ′ = [-1 V, -0.5 V] where the MOSCAP is in accumulation; whereas the light green is obtained by applying the fitting only in depletion. The distance between the intersection point, 1/ 2 = 0, for each of the fit ranges is small; from 0.1 V for the smallest to 0.9 V for the largest. The impact of such voltage shifts on the Dit profile is shown in Fig. 1b. These apparently small voltage shifts of can translate to a wide shift of the Dit curve, resulting in a wrong estimation of the interface quality.
Therefore, for obtaining the constant , the fitting of ′ vs 1/ 2 must be performed in the depletion region only, which requires a precise selection of the fit range for each device under test.

Analysis of Quasi-Static Capacitance-Voltage Setup Parameters
In order to calculate ( ) and proceed with the C-ψs method, a quasi-static capacitance-voltage measurement is required. We have studied the sensitivity of the measurement with respect to the selected ramp-rate (V/s), which is one of the main setup parameters in a quasi-static measurement system. Moreover, we have investigated the impact of using three different setups for the CQS measurements on the Dit extraction.
The ramp-rate (V/s) in a quasi-static measurement represents a trade-off between the resolution of the voltage sweep and the noise in the capacitance value [7]. This is illustrated in Fig. 2a showing the quasi-static capacitance (CQS) measurements with three different ramp-rates: 0.1, 0.5 and 1 V/s, respectively. Applying the C-ψs method for each of the ramp-rates, we observe that closer to the conduction band, there is a deviation of the Dit extracted for the 0.1 V/s ramp when compared to the other two values. This originates from the increasing noise in the measured discharge capacitance that becomes more prominent at low ramp-rates.

Silicon Carbide and Related Materials 2021
capacitance curves measured with the MFIA Zurich Instruments system that were analyzed using the high-low capacitance method [8].
Taking into consideration the sensitivity of the surface potential calculation as well as the ramprate effect previously discussed, we applied the C-ψs method and compared the Dit distribution from the measurements performed with the three quasi-static systems, Fig. 3b. We observe that for energies higher than EC-0.25 eV, the results of the three quasi-static setups are matching. However, due to the small differences in lower capacitance, and lower voltage values, the Dit distribution shows a different behaviour in the energy below 0.25 (eV) for the the Keysight B1500A compared to the results from the Keithley 595 QS CV Meter and the Keithley 4200A-SCS. Moreover, Fig. 3b includes the Dit results obtained with the high-low technique [8], which, as expected [4], underestimates the density of interface traps.

Summary
In this work, we have studied how the choice of the quasi-static CV setup and selected parameters for applying the C-ψs method influence the evaluation of Dit. Capacitance-voltage measurements of 4H-SiC n-type MOS capacitors show that the calculation of the surface potential can be a strong source of error if the depletion region is not well identified during the extraction of the integral constant . We assessed the influence of ramp-rate in the quasi-static measurements and observed that its impact is more prominent for lower values of energy due to the increasing relative noise. Finally, we compared three commonly used quasi-static systems, finding differences in their Dit distribution, more noticeable for lower energies. Further studies are needed to ascertain the optimal system and setup for the application of quasi-static methods.