Gate Bias Effects on SiC MOSFET Terrestrial-Neutron Single-Event Burnout

Power devices are susceptible to failure by terrestrial neutron single-event burnout (SEB) while in the high-voltage blocking state and above a VDS threshold for that device. Typically, the SEB failure rate is measured at a high blocking voltage, with the source and gate at ground potential. Here the effect of a negative gate bias, commonly applied during MOSFET switching to the blocking state, on the SEB failure rate is examined. It is observed that the SEB failure rate is only weakly dependent on the negative gate bias, because it does not significantly affect the peak field in the drift region where avalanche breakdown is initiated. A negative gate bias of -8VGS in the device blocking state at 1100VDS only results in a 6% increase in the MOSFET SEB failure rate.


Introduction
All power devices are susceptible to failure by terrestrial neutron single-event burnout (SEB) in the high drain bias (VDS) blocking state, above a VDS threshold for that device. This had been discovered initially for Si-based power devices [1,2], and more recently shown for SiC diodes and MOSFETs [3][4][5][6][7]. Typically, the SEB failure rate is measured at a high blocking voltage with the source and gate at ground potential. In this study the effects of a negative gate bias, while at high VDS, on the SEB failure rate are examined, to better match conditions of MOSFETs switched to the off-state using a negative gate bias.

Experimental and Results
Neutron SEB testing of MOSFETs has been performed at Los Alamos National Laboratory (LANL) using their spallation neutron source, as described in [6]. Groups of 12 devices are tested at given VGS and VDS bias conditions (all at 25°C), run until some or all the devices fail, and the failure time is correlated with the neutron fluence to determine a neutron fluence per fail. Fresh sets of 12 parts are mounted for each test at given VDS and VGS values. At very low VDS, only a few devices may fail because the test time needed is very long if the FIT rate is low; while at VDS closer to the rated voltage the test is typically run until all devices in the group fail. The failure rate is converted to the sea level neutron flux level, and the overall FIT rate is obtained for each group using the failure data for all the failed parts in the group, as described in JEP151 [8], and modeled with a trend line as presented in [9]. TCAD simulations of the MOSFET gate field under the various device bias conditions have also been performed to demonstrate electric field effects of the applied bias conditions. The TCAD model has Fowler-Nordheim tunneling enabled, and both hole and electron carriers. The TCAD modeling is not meant to describe the SEB event, but only to show the oxide and SiC fields under the SEB test conditions.
Presented here are results from Wolfspeed 1200V 16mohm SiC MOSFETs (C3M0016120K, Gen3), measured under neutron irradiation at LANL. Figure 1 shows the mean failure in time (FIT, fails per billion device hours) scaled to the NY city sea level average flux value, from groups of 12 devices tested to failure at each VDS condition, at VGS = 0V and room temperature. The points on the graph are the FIT rate obtained from all the failures in each VDS group [8]. The SEB failure for these devices follows trends with VDS typically observed for vertical power devices [5,7,9], indicating that below a given VDS value failure rates are exceedingly small. The effects of negative gate bias on the mean failure rate are shown in Fig. 2 for the Gen3 1200V 16mohm devces. The recommended gate turn-off voltage for this device is -4V, while the minimum rated gate bias is -8V. The result of decreasing the VGS from 0V to -8V on the mean FIT rate at 1100VDS reveals there is overall a small increase in the failure rate as the negative gate bias increases, but the effect is small. The SEB failure rate on average appears to increase about 1% per volt of -VGS applied.
To understand better the effect of the negative gate bias on the device, TCAD MOSFET simulations of these planar devices (half-cells shown) have been used to compare the SiC and gate oxide fields under 1200V VDS conditions, and at VGS of either 0V or -8V. As shown in Figs   to the gate oxide region and the SiC JFET region. Note in Fig. 4 that the gate oxide in the left edge of the image near the arrow (the center of the JFET region in the full device cell) has reached a higher field, but the field in the drift itself is relatively unchanged. To demonstrate this more clearly, Fig. 5 shows the E-field versus depth through a cutline along the JFET center (left edges of Figs. 3 and 4), from the gate down through the SiC drift. The fields in both the oxide and SiC at the JFET center increase as VGS increases in the negative bias direction. The peak oxide field and SiC peak JFET field just under the oxide increase ~9% when VGS is decreased from 0V to -8V. The fact that this closely matches the observed SEB failure rate increase with VGS indicates a correlation between the gate bias and the SEB failure rate. Fig. 5 shows that the field in most of the SiC drift layer, below the JFET region, is unaffected by the applied gate bias, and is higher than the JFET field, due to the P-well shielding of the JFET region. Note that the gate oxide field under 1200VDS blocking and -8VGS obtained in these TCAD simulations is lower than the typical MOSFET onstate gate oxide field, which is about 4MV/cm for a 15VGS bias. To better understand the effects of the VDS and VGS bias, the simulated JFET peak SiC field (just under the oxide at the JFET center) and peak oxide fields in the center of the JFET gap are shown in Fig. 6 as a function of the VDS value, for VGS values of either 0V or -8V. The negative gate bias increases the oxide field and the SiC field at the JFET center, for all VDS values. The results in Fig.  6 show that the electric fields in the JFET region with VDS of 1100V and VGS of -8V are equal to the electric fields obtained with VDS of 1360V with VGS = 0V. If the SEB failure were controlled by the JFET fields alone, then at 1100VDS, applying -8VGS would result in a similar SEB rate to that at 1360VDS with VGS = 0V. From Fig. 1 that would indicate that the SEB rate should increase ~8X when -8VGS is applied; but from the results in Fig. 2 this is clearly not the case. Only a 6% increase in SEB is observed when increasing the VGS from 0 to -8V at 1100VDS.
Considering the rate of SEB failure observed from VDS and VGS changes in Figs. 1 and 2, and the electric field simulations, the SEB failure rate is clearly more strongly dependent on VDS than VGS, in the valid ranges of device operation. The drain field effects of the applied VDS dominate the SEB failure rate overall because the locations of the device going into avalanche breakdown are controlled primarily by the drain bias. The effect on avalanche voltage of field changes at the top of the JFET region due to VGS effects are very small. Note that the peak SiC fields where avalanche breakdown would be initiated are below the P-shielding region (in Figs. 3 and 4), which is not significantly affected by the applied VGS. The electric field in the JFET region due to applied gate bias would only affect the SEB rate if it changes the electric field where the field peaks occur (making avalanche breakdown more likely), which it does not.
These results, which indicate that the JFET region is not a significant contributor to SEB failure, is in general agreement with other results [5,6] which show that the failure rates of SiC diodes and SiC MOSFETs are similar when the data are properly scaled to device active area and drift field, using avalanche breakdown field as a normalization factor. Device turn-off with negative VGS poses no significant SEB risk, because the SEB failure rate is dominated by the applied drain bias.

Summary
The measured SEB failure data shows that applying -8V VGS at 1100V VDS only results in a 6% increase in the SEB failure rate. This generally agrees with the TCAD simulations showing that the oxide field and peak SiC field in the JFET center only slightly increase with negative VGS applied. The effects of the applied VDS on SEB failure rate are much larger than the effect of applying a small negative VGS. The peak SiC fields, which determine the avalanche voltage, are in the drift region below the JFET region (in the P-shielding region), and these are not significantly affected by the applied VGS. Thus, the SEB failure is dominated by the effects of the drain bias, and gate bias effects are minimal.