Investigations of Short Circuit Robustness of SiC IGBTs with Considerations on Physics Properties and Design

The commercial success of silicon carbide (SiC) diodes and MOSFETs for the automotive industry has led many in the field to begin developing ultra-high voltage (UHV) SiC insulated gate bipolar transistors (IGBTs), rated from 6 kV to 30 kV, for future grid conversion applications. Despite this early interest, there has been little work conducted on the optimal layout for the SiC IGBT, most early work seeking to overcome difficulties in fabricating the devices without a P+ substrate. In this paper, numerical TCAD simulations are used to examine the link between the carrier lifetime of SiC IGBTs and their short circuit capability. For the planar devices, simulations show that increasing carrier lifetime from 1 to 10 μs, has not only a profound effect reducing on-state losses, but also increases short circuit withstand time (SCWT) by 39%. Two retrograde p-well designs are also investigated, the optimal device for SCWT having a 100 nm channel region of 5×1016 cm-3, with this increasing to a peak value of 2×1018 cm-3, in a 700 nm region beneath the channel.


Introduction
The electrical and thermal properties of silicon carbide (SiC)have made it an excellent candidate for high power applications. Ultra-high voltages (UHV) 4H-SiC devices rated at 10 kV and above are an attractive choice for HVDC converters, as to reduce the number of devices required in, for example, voltage-source converters [1,2]. Despite the optimization to gain better on-state performance and lower switching losses, the short circuit robustness of SiC IGBTs needs improving. The impact of a number of the state-of-the-art IGBT developments to date are explored in a series of benchmarking simulations.

Fig. 2
The p-well doping concentration of the retrograde planar devices, the RG-HD design coming from process simulation.
To begin, baseline 10 kV planar IGBT geometry has been implemented in the Sentaurus TCAD platform, its layout depicted in Fig.1. The baseline models are then adapted, with the p-well design and the impact of the lifetime τn. For the baseline models, the anode side of the structure is a fieldstop design with a 3 µm, 1×10 19 cm -3 p+ collector and a 1 µm, 1×10 17 cm -3 N-buffer. The cathode side employs a planar gate structure with an n-doped enhancement region. Due to the inherent poor SiC channel mobility, appropriate interface models are necessary and a realistic SiC/SiO2 trap profile with increasing trap concentrations at the edges is employed [3]. This strongly affects the channel mobility due to scattering mechanisms at the interface (i.e., acoustic, surface roughness, coulomb scattering [4]). Retrograde p-well is historically proposed for the high-density Si-based CMOS technology with later studies reporting an improvement in the latching performance compared conventional p-well design [6]. Two retrograde (RG) p-well designs are compared, their doping profiles shown in Fig. 5. They both have a 0.1 µm deep, 5×10 16 cm -3 channel region. Beneath this, the "RG-box" variant features a 0.7 µm, 5×10 17 cm -3 uniform box-profile doping. The second "RG-HD" variant features a higher doping, peaking at 2×10 18 cm -3 , which has been designed in the process simulator and verified experimentally. Both implementations are simulated with τn set to 1 µs, 10 µs and 20 µs. Following analysis of the static characteristics, the short circuit robustness of the variants is investigated via a short-circuit switching simulation. In order to obtain informative results, the p-base current is isolated from the emitter current at the cathode side of the device by adding an additional separate base contact to monitor the current flow at the top of the device. Fig. 3 shows the short circuit test circuit, in which a 5000 V DC pulse is applied to the IGBTs' collector for increasing duration until the device breaks down (via parasitic n+/p-base turn-on and eventual thermal runaway). The parasitic inductance (L1) for the test setup is 180 nH.

Static Results
The forward conducting characteristics of the planar IGBT designs, are shown in Fig. 4; Fig. 5 shows their excess carrier density in the drift region at 100 A/cm 2 . As demonstrated experimentally [5，6， 7], the on-state losses are heavily affected by the underlying carrier lifetime and the distribution of the charge. At τn=10 µs the carrier density of the 100 µm drift layer with a RG-box p-well approaches relative saturation. An RON,SP.DIFF of 12.2 mΩ.cm 2 is recorded, the VON is 5.6 V at 100 A/cm 2 , and the JON is 60 A/cm 2 at 300 W/cm 2 . The on-state characteristics are largely unaffected by the different retrograde p-well designs.

1) Planar IGBT: Effect of p-well design
Short circuit switching simulations demonstrated the advantage of the RG-HD p-well design in withstanding a short circuit fault condition. Fig. 7 shows the transient characteristic under shortcircuit conditions with the gate pulse left on until latch up and destruction. This occurred after 6 µs for the RG-box p-well device whereas the optimised device lasted for over 25 µs. The reason for this improvement in the RG-HD p-well design is due to its higher doping (Fig. 2) beneath the channel, which provides a low resistance path for hole current to the emitter. Fig. 8 shows the electron current density of the RG-box structure during this period. As minority carriers, in the p-well, the electron density is seen to exceed 5×10 14 cm -3 at tSC = 6 µs, suggesting that the n+/p-base junction is forward biased and thus triggering the junction failure, with the device eventually failing due to thermal runaway.

2) Planar IGBT: Effect of carrier lifetime
For the SiC IGBTs, like SiC MOSFETs [8,9], SRH generation is responsible for an increase in leakage current. Reducing carrier lifetime enhances the SRH generation in the depletion region of the p-base/n-drift junction, and the holes generated flow through the p-base/n-drift junction, leading to an increase in base leakage current. For the RG-HD p-well structure the lifetime effect is significant. From Fig. 9, an increase in τn from 1 µs to 10 µs brought about an increase in the SCWT of 39% from 18 µs to 25 µs. This underlines that a lifetime enhancement procedure (e.g. via surface oxidation [10]) would benefit both ON-state performance and short-circuit capability. Similar to the concept of current saturation, the SRH generation rate reaches a minimum by τn=10 µs, and no further improvement in the SCWT occurs above this value.

Summary
The static performance and short circuit robustness of 10 kV SiC IGBTs was investigated. The planar structure is with much improved short circuit robustness, in a similar fashion to silicon devices. However, in contrast to silicon bipolar devices, SiC IGBTs static and dynamic performance does benefit from lifetime enhancement. A highly doped retrograde p-well doping profile is necessary in order to improve on-state and short circuit robustness.