DC Modeling of 4H-SiC nJFET Gate Length Reduction at 500°C

The development of robust, high-performance integrated circuits (ICs) will enable numerous potential NASA missions of current interest, including long-duration robotic missions exploring the 460°C surface of Venus. Currently, NASA is looking towards SiC-based devices to provide such a solution. However, the current NASA silicon carbide (SiC) JFET device with a channel length of 6 μm (recently fabricated Gen. 11 ICs) limits mission-relevant circuit capabilities. In this study, we combined experiments with simulations to explore two straightforward fabrication strategies (shallow n−and extended n+) to reduce the SiC JFET channel length while maintaining the turn-off behavior needed to realize 500°C circuit operation. COMSOL Multiphysics was used to simulate the transfer characteristics and maximum potential below the gate of a 4H-SiC nJFET at 500°C, and a 1 μm gate length nJFET with turn-off performance comparable to the state-of-the-art is suggested.


Introduction
NASA is exploring silicon carbide, a wide band-gap semiconductor material capable of operating at high temperatures, to create robust, high-performance electronics that can work in harsh environments (high radiation levels and high Venusian surface temperatures) [1]. A step towards this goal is to substantially reduce the channel length of 4H-SiC nJFETs recently fabricated in the Gen. 11 ICs [2] from 6 µm to 1 µm. There are various strategies to reduce the gate length and feature size of a 4H-SiC JFET [3]. This paper presents a study on reducing the gate length of a lateral nJFET by comparing and contrasting two fabrication strategies. The first fabrication strategy uses a shallow self-align nitrogen implant (SN, Fig. 1a) along the device's top surface but not below the gate combined with a highdose phosphorous implant directly below the source and drain contacts, while the second strategy ( Fig. 1b)  x = 0 x = 0 n n Fig. 1: Schematic for the 4H-SiC nJFET device with two doping strategies: a) self-align nitrogen (SN) and b) extended phosphorous (EP). The different layers are p substrate (blue), p − sub-channel layer (light blue), n epitaxial layer (green), n + source and drain epilayer (dark green), n − nitrogen self-align implant (light green), and p + gate epilayer (dark blue). edges. These two doping strategies are explored in order to shorten gate length while maintaining or improving nJFET's turn-off performance. For this study, twelve variations of lateral epitaxial 4H-SiC nJFETs with different fabrication strategies, gate lengths, and geometric properties were simulated in COMSOL. However, only a few key results are shown for brevity.

Methodology
Experiment. The first fabrication strategy uses a shallow self-align nitrogen implant (Figure 1a) along the device's top surface but not below the gate combined with a high-dose phosphorous implant directly below the source and drain contacts. The SN device structure is consistent with experiments by NASA GRC in prototype IC generations 10 and 11 [2]. The experiments were performed at 500°C and the n epilayer thickness of the device was 0.42 µm. Simulations. The 4H-SiC nJFET was simulated using COMSOL Multiphysics v5.6 with the semiconductor module. The material parameters and the physical models used to simulate the electrical potential and carrier concentration profiles were taken from Ref. [4]. The models used to simulate the physics for nJFET were: Auger recombination, Shockley-Read-Hall (SRH) recombination, incomplete ionization, and low-field mobility. The details of the model, its implementation, and the simulation protocol for simulating a 4H-SiC nJFET in COMSOL are available on reasonable request.

Results and Discussion
Before the gate length reduction studies, the turn-off and transfer characteristics of the COMSOL simulations were validated with the measured data of a 4H-SiC nJFET with the SN strategy at 500°C, and the results are presented in Fig. 2. The threshold voltage (V th ) were computed using the saturation extrapolation technique. Using this method, the simulated (experimental) values of V th are computed to be −9.83 V (−9.66 V), when V s = −25 V, and −11.26 V (−10.68 V), when V s = −15 V. While the values of I dss are 13.11 µA µm −1 (11.46 µA µm −1 ) and 15.03 µA µm −1 (13.02 µA µm −1 ), respectively.
The simulations show that the V th is similar for both the doping strategies, while the saturated drain current (I dss ) is about 10% higher for the EP strategy. The higher value of I dss results from the deeper and higher concentration of dopants used in the EP strategy. The fit with the experiments validates the 4H-SiC nJFET model implementation and the simulation protocol. Note that the high  value of the turn-off current floor in the experiments was a result of the package leaking current [5].
Thus, the simulation model parameters were not modified to quantitatively match the experimental off-state current floor. Table 1 compares the DC electrical performance of nJFETs with decreasing gate length for each of the doping strategies. These results are consistent with short-channel device physics reported in the literature for other types of field-effect transistor structures. In other words, the ability of the negative gate bias to impose a higher potential barrier to inhibit electron transport from source to drain diminishes as channel length shrinks. This barrier reduction is evident in Figs. 4a-c. However, thinning the n epilayer channel does increase the potential barrier, as seen in devices as seen in devices #6* (Fig. 4d) and #7* (not shown). Note that this approach significantly tightens the processing margins and risk associated with still-maturing SiC epilayer thickness tolerance/control as well as the gate finger etch depth. While increasing the p-layer doping might also improve device turn-off performance, this would also increase the magnitude of substrate body bias effect that would present additional circuit design challenges. Another experimental risk of the EP strategy is the higher electric field and leakage currents it might impose where the EP implant borders the edge of the gate. While this has not been a problem in experimentally realized SN devices operated at 500°C, the increased doping of the EP devices could raise the peak electric field in this region. Therefore, a further study of the EP approach is planned to elucidate its leakage and breakdown properties.  (d) Device #6* (EP) Fig. 4: The value of the maximum potential below the gate for the selected devices (1, 2, 4, and 6) listed in Table 1. Other simulation parameters were: V s = −25 V, V d = 20 V, and T = 460°C.

Conclusions
This paper explored design strategies to optimize the lateral-gate-length of a 4H-SiC nJFET operating at 500°C using COMSOL multiphysics. We compared the turn-off characteristics of two fabrication strategies, SN and EP, with gate length decreasing from 6 µm to 1 µm. The results show that the deeper and high concentration of phosphorous dopants combined with a thinner n epitaxial channel led to a better turn-off response when decreasing gate length. Simulations resulted in a 4H-SiC nJFET design with a 1 µm gate length without compromising the turn-off performance.