Comparative Performance Evaluation of Conventional and Superjunction Vertical 4H-SiC High-Voltage Power MOSFETs

We evaluate and compare the static and dynamic performances of four different 4H-SiC power MOSFETs (Conventional DMOS and UMOS, Superjunction (SJ) DMOS and UMOS FETs) from 0.6 to 10kV. The static on-state performance is determined by analytically calculating the specific on-resistance (RON,sp), while the dynamic switching performance is determined by extracting the specific gate charge (QG,sp) and switching energy loss per cycle (Esw,cycle) using 2D device simulations. It has been found that the SJ UMOS FET exhibits at least a 31% (up to 53% at 0.6kV) reduction in the RON,sp · QG,sp Figure-of-Merit (FoM) compared to the SJ DMOS FET within the breakdown voltage rating range studied.


Introduction
4H-SiC has a 10× higher critical electric field than Si, making it possible to achieve high voltage power devices with a much smaller (1000x) specific on-resistance (RON,sp) than Si-based devices at the same breakdown voltage (BV). Besides, superjunction (SJ) devices have better conduction performance over conventional devices due to a lower specific on-resistance in the drift layer, resulting in a better trade-off between RON,sp, and BV and hence lower conduction power loss [2]. In this paper, the conventional vertical planar DMOS and trench UMOS FETs, and their SJ counterparts, in 4H-SiC, in the blocking voltage range between 0.6 to 10kV, are examined and compared in terms of their static and dynamic performances, determining quantitatively which transistor to have the best performance.

Device Design
The schematic cross-sections of the four power MOSFETs considered are shown in Figs. 1 to 4, with the unit cell pitch of 6 and 3μm for DMOS and UMOS structures, respectively. The conventional 4H-SiC devices are designed using t, and ND dependence on BV [3], while the SJ devices are designed according to [4] for the desired BV ratings. In Table 1, the drift layer thickness and the doping of the conventional UMOS and DMOS FETs, while the structural parameters for SJ FETs is at constant aspect ratio (t/W=10). The electron inversion and accumulation mobilities are assumed to be 15 and 200 cm 2 /V.s respectively for DMOS. However, the inversion mobility for UMOS FETs is 66cm 2 /V.s because of the different crystal orientations. The specific on-resistance components are depicted in Fig 5 and 6. All of them are calculated using the structural dimensions, doping, and mobility of the corresponding regions. The three main components are the channel region (Rch,sp), the JFET region(s) (RJFET (1,2)), and the drift region (Rdrift,sp) for the conventional devices. However, for SJ devices, the drift region has a lower resistance because of a higher pillar doping compared to conventional devices. At lower BVs, the resistance of the channel region dominates, while the drift region dominates at relatively BVs. Consequently, at lower BVs, we expect that the conventional and SJ devices will have almost the same specific onresistance (RON,sp) due to the channel region, however, at higher BVs, SJ devices will deviate from the conventional devices and exhibit a significantly lower specific on-resistance (RON,sp).
For the dynamic characteristics, the specific gate capacitance is extracted from a 2D device TCAD simulator (Sentaurus) for each device at each BV rating. From the switching simulations, the gate current iG is integrated over the time to obtain QG,sp. Furthermore, switching energy loss per cycle (Esw/cycle) are extracted. The switching circuit is shown in Fig. 7, where the device is scaled with the appropriate resistive load to achieve the same drain current (ID = 10A) and (Von = 1V) through and across each device.

Results and Discussion
In Fig. 8, the RON,sp and BV trade-off for SJ FETs is better. For SJ FETs, the trade-off is RON,sp ∝ BV 2 and RON,sp ∝ BV for constant asepct ratio and constant pillar width respectively, while it is RON,sp ∝ BV 2.3 for conventional FETs. In Fig. 9, RON,sp is reduced by 89 and 78% for SJ UMOS and DMOS FETs respectively, compared to their conventional counterparts at 3300V, due to a lower Rdrift,sp, achieving 99% reduction at 10kV, while QG,sp reduction is 8 and 20% at all BV ratings. The lower RON,sp of UMOS devices is due to a higher channel density, hence lower Rch,sp. In Fig. 10, SJ UMOS exhibits longer turn-off time, hence, higher switching energy losses per cycle due to higher QG,sp. As illustrated in Fig. 11, the SJ UMOS FET with the narrowest pillar width [5] exhibits the best performance as it has a Figure-of-Merit (FoM) (RON,sp · QG,sp) reduction of 24, 47, 90, 95, and 99% compared to conventional UMOS at 0.6 to 10kV ratings respectively, while it is 53, 51, 49, 40, and 31% in SJ DMOS at the same BV ratings respectively. The FoM reduction is decreasing at higher BV because the pillar resistance dominates at higher BVs. Unlike Si, 4H-SiC has a significant specific drain charge QD,sp because of its heavier doping and shorter thickness at the same breakdown voltage. On the other hand, SJ devices exhibit sharp CV characteristics, enabling them to have very small QD,sp, and lower switching losses compared to conventional devices. SJ UMOS has higher switching losses due to an average of 60% higher QG,sp compared to SJ DMOS, however, it has a significant on average reduction of 50% in RON,sp, achieving the lowest FoM.

Summary
In summary, the SJ UMOS FET has the best performance in terms of the lowest RON,sp · QG,sp FoM with at least 31% reduction compared to SJ DMOS at all BV ratings, which infers to have the lowest total energy loss (conduction and switching losses).