Impact of Device Design Parameters on 15 kV SiC MOSFETs

Experimental results from 15 kV-rated SiC DMOSFETs developed by GeneSiC Semiconductor are presented. A breakdown voltage of 16.7 kV is recorded, with < 200 nA leakage current at 15 kV. RDS,ON in the range of 4-5 Ω, 12-15 Ω or 50-75 Ω were measured on MOSFETs with chip sizes of 25 mm2, 16 mm2 and 9 mm2, respectively, with a lowest specific RDS,ON of 238 mΩ-cm2. The impact of MOSFET channel length and JFET width on the device performance is elucidated. Single-pulse avalanche energy = 22.1 J/cm2 and tAV=18.2 μs is achieved. VG-+20 V gate stress applied at 175°C showed good VTH stability with only a small 200-300 mV increase during the initial stages of the stress time.


Introduction and Experimental Details
Ultra-high voltage (> 10 kV) SiC transistors will be a key enabling technology for smart-grid solidstate transformers [1], traction device and renewable energy systems, power supplies for electron guns, and DoD applications [2]. In this paper, we present experimental results obtained on SiC planar MOSFETs developed by GeneSiC Semiconductor on 150 µm/4.5E14 cm -3 thick N-drift layers. Different die sizes with total chip areas of 9 mm 2 , 16 mm 2 and 25 mm 2 were fabricated. A planar DMOSFET device structure was employed, with different JFET and MOSFET channel lengths. A 50 nm thick gate oxide was used. The device fabrication was conducted using GeneSiC's established process used for fabricating lower voltage rated SiC DMOSFETs. Selected die were packaged in custom packages for high-temperature and UHV characterization.

Static Electrical Characteristics
Breakdown Voltage: A breakdown voltage of 16.7 kV was measured on 16 mm 2 MOSFETs fabricated on 5E14 cm -3 drift layer (Fig. 1a). The simulated unit cell breakdown voltage is shown in Fig 1b. A worst case breakdown voltage, assuming 20% higher drift doping and 10% higher drift thickness is also shown in Fig. 1b.  The measured breakdown voltage is close to the 1-D avalanche breakdown voltage for the 150 µm/5E14 cm -3 N-epilayer, which is an indication of a robust device design. A sub-200 nA drain leakage current is observed at the rated 15 kV blocking voltage.
Output Characteristics: A comparison of output characteristics measured in the 1 st and 3 rd quadrants on 25 mm 2 SiC MOSFETs (active area = 7.4 mm 2 ) with different JFET widths is shown in Fig 2a. The MOSFET with JFET width of 2.5 µm shows the presence of a "knee voltage" due to a potential barrier in the JFET region, which is clearly absent for the MOSFET with JFET width of 3.0 µm. RDS,ON values of 4.4 Ω and 5.2 Ω are extracted at VGS=20 V and ID = 2 A, in the 1 st quadrant for the different JFET width die, which corresponds to RDS,ON-SP of 324 mΩ-cm 2 and 383 mΩ-cm 2 , respectivelythe 1-D calculated N-drift layer resistance is ~ 220 mΩ-cm 2 , for comparison. The RDS,ON for the two devices in the 3 rd quadrant (Fig. 2b) are 252 mΩ-cm 2 and 259 mΩ-cm 2 , respectively. The 3 rd quadrant RDS,ON is closer to the calculated resistance for the N-drift layer, with almost no difference between the two devices with different JFET widths. Since the body-drift p-n junction is forward biased in the 3 rd quadrant, these observations indicate that a significant portion of the total 1 st quadrant RDS,ON can be attributed to the resistance in the JFET region, for these devices. The output characteristics measured at 175°C is shown in Fig. 2b. The RDS,ON at 175°C increases by a factor of three, when compared to the room-temperature value.  Fig. 3. A clear reduction of RDS,ON with increasing JFET width is observedthe minima in the RDS,ON lies beyond the range of JFET widths explored in this study. A lowest RDS,ON of 238 mΩ-cm 2 is extracted for the widest JFET width explored in this studythis is close to the theoretical limit. There was minimal impact of MOSFET channel length on the output characteristics (not shown). The peak gate oxide field was kept below 4 MV/cm for all device designs explored in this study.

Third Quadrant Characteristics:
The output characteristics in the 3 rd quadrant are compared at room-temperature for 16 mm 2 MOSFETs (active area = 2.1 mm 2 ) at different gate biases in Fig. 4a, and with different channel lengths, in Fig. 4b. A cross-over current is clearly visible in Fig. 4a, above which zero gate bias results in higher ISD than the case when VGS=20 V. When the MOSFET channel is kept off (zero gate bias), the ISD is primarily conducted through the p-n junction in bipolar mode, with conductivity modulation of the N-drift layer. When the MOSFET channel is fully turned on (VGS = 20 V), a significant portion of the ISD is conducted by the majority carrier electrons through the MOSFET channel, and less current is conducted by the body diode in bipolar mode, which results in a higher differential on-resistance (or lower ISD) at a given drain bias. The MOSFET with the longer channel (Fig. 4b) shows a more pronounced bipolar action when compared to its shorter channel counterpart, since the higher channel resistance pushes more current through the p-n junction. There is no impact of the MOSFET channel length in the 1 st quadrant output characteristics (not shown) which are largely dominated by the high resistance of the 150 µm thick drift layer. At 175°C (Fig.  4c), the Aluminum acceptors in the P-Well are almost fully ionized [3], and this results in a more stark contrast between the zero gate bias and 20 V gate bias output curves for either device. Fig. 4c shows that operating the 15 kV MOSFET at 20 V gate bias can result in a positive temperature coefficient of ISD, whereas operating the same device at zero gate bias can result in a negative temperature co-efficient of ISD due to the aforementioned competing mechanisms.  Transfer Characteristics: The transfer I-V characteristics of a 25 mm 2 MOSFET at 25°C and 175°C are shown in Fig. 5. A gate threshold voltage (VTH) of 3.2 V is measured at ID = 1 mA at roomtemperature, which drops to 1.8 V at 175°C. In the 10 nA -1 µA ID range, an average sub-threshold slope (SS) of 240 mV/decade is extracted at 25°C, which drops to 206 mV/decade at 175°Ca lower SS at higher temperatures (and at lower drain bias) results from an exponentially decreasing acceptor trap density when moving away from the conduction band edge of SiC, towards the mid-gap. The density of interface traps is extracted from the room-temperature SS as 1x10 13 cm -2 eV -1 in weak inversion, using the equation provided in [4].

Saturation Current Characteristics:
The saturation current (ID,SAT) characteristics measured on two 15 kV MOSFETs with different channel lengths (Fig. 6). A 20% lower ID,SAT was measured at VDS=600 V, with near-identical RDS,ON under operating conditions. A lower ID,SAT is beneficial for increasing short-circuit withstand time, since it reduces the power dissipation during the short-circuit event. The short-circuit robustness of these devices will be reported elsewhere.
High-Temperature Gate Bias Stress: Several 15 kV SiC MOSFETs fabricated in this work were stressed for 60 hours at VGS = +20 V in a 175°C oven. The evolution of the VTH over time is shown in Fig. 7. After an initial increase, the VTH saturates for the remainder of the stress time, similar to the 1200 V SiC MOSFETs reported in [5].

Unclamped inductive switching (UIS):
Unclamped inductive switching (UIS) was performed on a packaged 15 kV MOSFET at a peak drain current of 2.95 A (141 A/cm 2 ) with a 115 mH inductor at room-temperature, with VGS = 20 V and VDD = 250 V. We could not measure the drain voltage during the UIS waveform, due to equipment limitations for measuring such a high voltage. A singlepulse avalanche energy (EAS) ≈ 22.1 J/cm 2 was achieved before the device failed catastrophically. A peak drain voltage of 18.9 kV can be inferred from the inductor discharging waveform (Fig.8), which is in line with the static breakdown voltage reported in Fig. 1.

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Silicon Carbide and Related Materials 2021