Clamped and Unclamped Inductive Switching of 3.3 kV 4H-SiC MOSFETs with 3D Cellular Layouts

This work presents for the first time a comparative numerical study on the performance of planar 3.3 kV SiC MOSFETs during clamped and unclamped inductive switching for various cell layouts and pitches. It is demonstrated that despite its larger on-state losses, the atomic lattice layout (ALL) incurs smaller switching losses than the stripe and the circular designs for all examined cell pitches. Conversely, while the ALL does turn off earlier than the other layouts during UIS, the decrease in the peak lattice temperature that it brings is predicted to be marginal if just a single unit cell is considered.


Introduction
The advantageous material properties of SiC have recently made 4H-SiC MOSFETs attractive for various power applications. In particular, the superior performance trade-off (between the specific resistance Ron * , the breakdown voltage Vbr, and the total switching time tswitch) that SiC MOSFETs offer compared to Si devices have allowed for improvements in the efficiency and the reliability of the power system, enabling operation at a higher junction temperature [1]. Nevertheless, despite these advantages of the semiconductor, the increased power density in SiC MOSFETs can aggravate the heat extraction process and hence compromise the reliability of the packaging and the metallisation.
In this context recent studies have looked into the possibility to alleviate these issues by using advanced cellular layouts [2,3]. However, while the static behaviour of these 3D designs is now well understood [2][3][4], the variation of their dynamic response during both nominal and fault switching conditions, such as unclamped inductive switching (UIS), with the cell pitch Wcell requires further study. The latter case becomes particularly important at high Vbr ratings of 3.3 kV and above. That is why this work proposes a comprehensive numerical study on the electro-thermal performance of 3.3 kV planar 4H-SiC MOSFETs during both UIS and clamped inductive switching for three different cell layouts (stripe, circular, and the atomic lattice layout [4]) at a range of cell pitches.

Methodology
The layouts of the examined 3.3 kV designs can be observed in Fig. 1. Here the circular and the ALL are simulated in 2D by solving the drift-diffusion equations for the unit cell in cylindrical coordinates around their respective axis of symmetry. The drift region has a thickness of 30 μm and is doped n-type at 3x10 15 cm -3 , while the p-well is implemented using a retrograde profile matched to a process simulation [5]. A channel length of 300 nm is assumed, with the acceptor doping at the surface being ~ 2x10 17 cm -3 . The interface is described using the Dit distribution for the Si-face from [6] (assuming only acceptor states above the midgap level), along with a positive fixed charge density of 1.75x10 12 cm -2 . In turn, the p-short contact half-width is set to 2 μm. The cases with a different cell pitch are obtained by adjusting the width of the JFET region, while the termination area is neglected.
The above structures are implemented in Sentaurus TCAD [7] and are then inserted into the circuit in Fig. 2 (without the freewheeling diode for UIS mode). Here the unit cells are scaled so as to get an active area of 0.15 cm 2 . A default diode from the TCAD's in-built SPICE library in [7] is used for the clamped inductive switching case. Conversely, a fixed thermal resistance of 0.3 cm 2 K/W is placed at the drain for UIS mode. Unless otherwise stated, all subsequent results are for Wcell = 12 μm.

Results and Discussion
The performance of the above designs is first examined at nominal inductive switching conditions for an on-state drain current of 100 A/cm 2 . In agreement with [4], the circular design is found to have the lowest resistance of all layouts for typical values of Wcell ( Fig. 3 (a)). Conversely, the ALL attains a comparable Ron * only at larger Wcell due to its saddle junction, which increases the channel, JFET, and spreading resistances for small Wcell (although it also increases the breakdown voltage compared to the other layouts ( Fig. 3 (b)). Still, this drawback of the ALL should be less important at a higher Vbr rating (and JFET doping), where the drift region forms the dominant contribution to Ron * .
On the other hand, from Fig. 4 (a-b) it can be seen that the ALL (circular) attains the fastest (slowest) response of all layouts during both turn-on and turn-off (for a 12 μm cell pitch). In particular, the ALL exhibits a shorter Miller plateau during both switching instances. These results are confirmed by the C/V waveforms in Fig. 5, where the ALL's Cgd is an order of magnitude smaller than in the other designs. This drop of the Miller capacitance arises from the wider lateral extension of the depletion region brought about by the ALL's saddle junction (as seen by the sharper slope of Cgd at Vds ~ 0 V) and also from the smaller gate contact area (and hence weaker gate-drain coupling) of the ALL compared to the other designs. The ALL can hence be expected to display a smaller Cgd and lower switching losses also at other Wcell values. Nonetheless, the smaller Cgd of the ALL also leads to notably larger oscillations in the drain current Id at turn-off if the same gate resistance Rg is used for all layouts (Fig. 4 (b)). Thus, it may become necessary to employ a larger Rg so as to reduce dId/dt and hence obtain a cleaner turn-off waveform (albeit at the cost of increased switching losses).

Silicon Carbide and Related Materials 2021
The variation of the switching responses with Wcell can be seen in Fig. 6. Here the losses are computed using the electron current through the channel (hence power dissipation due to capacitive charging is neglected). It can be observed that both Eloss and the switching time tswitch (defined as the sum of the 0/95 % rise time of Vgs during turn-on and the time until the first zero-crossing of Id at turn-off) increase monotonically with Wcell for each layout due to the larger Cgd (and hence wider Miller plateau) of the structures with a bigger pitch. The ALL not only has the fastest response for all cases, but the reductions in Eloss and tswitch that it produces grow at larger cell pitches. At the same time, the amplitude of the observed oscillations falls as Wcell is increased (thanks to the larger Cgd). Conversely, at small Wcell the ALL's advantage in Eloss weakens and gets overruled by its larger Ron * .
The responses of the structures during UIS (with D1 removed) are now presented in Fig. 7 (a-c). Although the differences between the layouts are rather small as only a single scaled unit cell is considered, the ALL (circular) still clearly dissipates the inductor current Id faster (slower) than the others. This can be explained with the larger (smaller) breakdown voltage Vbr of the ALL (circular) (Fig. 3 (b)) due to its saddle (cylindrical) junction [4]. Indeed, since the voltage across the load L1 is -L1×dId/dt ≈ (Vd -Vdc), Id should fall faster in a layout with a larger drain voltage Vd. The more rapid turn-off of the ALL is found to compensate for the extra heating due to the larger Vds, allowing it to attain the lowest peak temperature Tmax (and Eloss). Nonetheless, this reduction is only ~ 10 K (≈ 2 %).
The same trend can also be seen at other cell pitches (Fig. 7 (d)). Here both the turn-off time tturnoff and the peak Tmax increase with Wcell for all layouts due to the corresponding drop of Vbr with Wcell.  Vbr, yet its Ron * becomes competitive only at large Wcell. The lowest (highest) degree of self-heating is again attained by the ALL (circular). Still, although the performance differences become somewhat clearer at larger Wcell (due to the greater variation of Vbr with the layout), the ALL's advantage during UIS (in case of a single unit cell) remains negligible.

Conclusion
In this paper the impact of the cell layout and the cell pitch on the switching speed and losses of 3.3 kV planar SiC MOSFETs has been investigated numerically. It has been shown that while the circular design attains the lowest Ron * , it incurs larger switching losses than the other layouts. At the same time, the ALL attains the smallest Eloss thanks to its reduced Cgd and hence becomes competitive for designs with a sufficiently large pitch. Conversely, the improvement during UIS due to the isolated effect of the ALL's unit cell is predicted to be marginal. In order to assess if this advantage of the ALL can become truly significant in a real device, the entire die needs to be considered in the analysis.

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Silicon Carbide and Related Materials 2021