On the Short Circuit Electro-Thermal Failure of 1.2 kV 4H-SiC MOSFETs with 3D Cell Layouts

In this manuscript, the short circuit (SC) capability of 1.2 kV vertical double diffused SiC MOSFET with different layout topologies is investigated. 3D finite element electro-thermal simulations have been carried out in order to assess the performance of five different cell topologies. It has been found that while the maximum drain current density observed during a SC event agrees well with the specific on-state resistance behaviour, the maximum temperature evolution in the unit cell follows the opposite trend. This behaviour can be explained by the relatively poor spreading of the carriers in the JFET region (of the ALL) at small cell pitches (~ 8um), which can lead to the formation of a filament with a high current density and heat generation.


Introduction
Initially manufactured for the 600 V range by Rohm in 2010 and immediately followed by the first commercial 1.2 kV 4H-SiC MOSFET from Cree, SiC MOSFETs are now commercially available in either discrete or module configurations mainly for automotive and traction applications. Regarding 1.2 kV 4H-SiC MOSFETs, manufacturers have opted for different cell designs (symmetric/asymmetric trench, planar etc.), in order to tackle issues related to the low mobility at the Si-face, dielectric reliability, gate charge hysteresis, NBTI and PBTI, and bipolar degradation [1][2]. Compared to Si-counterparts, SiC MOSFETs allow for an increased power density and maximum junction temperature (Tjmax), while improving the efficiency and reducing the size of the power electronic system. While the maximum junction temperature itself does provide a useful indication of the device's resistance towards abnormal electrical events such as unclamped inductive switching (UIS) and short circuit (SC), fast thermal transients due to the high-power density are often what limits the reliability of the device, the metallization, and the packaging material [3]. In this context, advanced unit cell topology could be beneficial in suppressing the contribution related to the channel resistance and reducing the fast dT/dt. In Si, the unit cell layout is known to affect several static (specific on-state resistance (RONS) and breakdown voltage BV) and dynamic (CGD/CGS ratio) electrical characteristics of the power MOSFET [4]. Nevertheless, to date, the impact of the cell layout on the short circuit (SC) performance has not been reported yet in the literature. Thus, this study presents a complete investigation on the thermal runaway failure mechanism for several SiC MOSFET layouts. This type of failure mechanism is obtained when the thermally generated carrier concentration exceeds the background doping concentration and the device reaches an intrinsic state with the formation of a low Ohmic current-path.

Methodology
The different cells analysed are displayed in Fig. 1(a-e). Circular and ALL have been solved by means of cylindrical coordinates. Conversely, the array and Hex layouts have been simulated by using 3D unit cells that account for 1/8 and 1/12 of the total cell. Ideal Neumann conditions have been applied to the geometrical boundaries. A layer of positive fixed charges (1.75x10 12 cm -2 ) has been added at the SiC/SiO2 interface. The drift (buffer) region's doping and thickness have been set to 10 µm (1 µm) and 1x10 16 cm -3 (5x10 18 cm -3 ). The implanted profiles have been matched from a process-based simulation, both the p+/n+ regions are 1µm long and the channel length is fixed at 300 nm for all the geometries. The threshold voltage is identical for all topologies analysed in this study.

Fig.1. Top views of (a) stripe (b) array, (c) hex, (d) circular, (e) ALL, (f) cross-section of the stripe.
The SC capability of each structure is examined through single pulse short circuit (type I) mixedmode simulations, using the circuit in Fig. 2(a). A single thermal interface has been added at the drain contact with a specific thermal resistance of 0.3 cm 2 K/W. This situation reproduces well the typical heat transfer configuration in which the top area of the device is less thermally conductive compared to the substrate. Reflective heat boundary conditions have been assumed at the geometrical boundaries of the device. For the purpose of this work, thermo-mechanical effects, convection and radiation heat exchange, gate oxide failure or cell-to-cell unbalances have not been accounted for [5].

Fig.2 Schematic circuit used for the SC (type I) simulations(a), top view conduction area (orange)
for circular and ALL which shows that the area SALL<SCIRC (b) and output IV at T=300K, VGS=15V(c).

Materials Science Forum Vol. 1062
In Fig.2(c), the simulated RONS for SiC devices reproduces well the experimental and theoretical trends observed in [1] for Si-devices, with the circular MOSFET outperforming the other layouts in terms of RONS. Similar ON-state performance (as well as SC performance in Fig.3(a) and breakdown voltage, not shown) can be observed for the array, hex, and circular layouts.
Note that the formation of the channel along the Si-face (x-y plane) allows for the variation of the channel mobility along the different crystal faces (which could affect the outcome of the comparison for trench-based MOSFETs) to be neglected. The structure's electrothermal response is described, using the classical thermodynamic model (Eq.1-3) [6][7].
This expression is based on the continuity equation, which relates the rate of change of the internal energy of the system (composed of the lattice and the carriers) to the energy flux due to conduction via Fourier's law, Joule and Thomson heating (second term), optical generation, and an additional term, which accounts for the energy's dynamic variation with the carrier density. The Peltier coefficient П here is computed assuming Thomson's second relation and Mott's formula for the Seebeck coefficient. The SC drain current density (JD) and the maximum and average lattice temperatures (Tmax, Tavg) for a 5μs SC pulse (CP=8μm) are shown in Fig. 3 (a-b). It can be observed that Tavg follows the same trend (with the cell's topology) as JD. This also agrees with the (expected) variation of RONS with the cell layout (shown in Fig. 2 (c)).
Conversely, Tmax varies in the exactly opposite way. The increased local heat generation in the ALL cell can be explained with the stronger (local) Joule heating effect (where QJoule= J 2 /σ as shown in Eq.3). Indeed, the ALL's smaller JFET area density (calculated in Fig. 2(b)) limits the spreading of the current and hence increases the (local) current density, effectively creating a current filament.  The cells' behaviour for different CPs is presented in Fig. 4 (a-d). Here Tavg correlates well with the peak short circuit current (JD_max) and the critical SC energy (Esc). Indeed, the higher Tavg of the circular reduces the SCWT due to premature thermal runaway. More interesting is the evolution of Tmax with CP, where a non-monotonic trend can be observed for the circular and stripe designs, but not for the ALL (Fig. 4 (c)). This differs from the variation of the JFET area density in Fig. 4 (a) and can be explained through examination of the temperature distribution in the top of the cell (Fig. 5).
In the case of the ALL, the peak temperature point lies deep inside the JFET region (and farther from the channel than in the other designs) for all examined CP (Fig. 5). This is a consequence of the smaller conduction area in the JFET region. At larger CP, however, the JFET component of RONS reduces monotonically, which allows for improved current spreading (in the JFET region) and hence slowly shifts the point of the peak current density (and of Joule heating) to the interface. Conversely, while a similar trend can be seen in the stripe cell, the depth (relative to the surface) of the location of Tmax is smaller (due to the larger JFET area). In fact, for the circular, the point of Tmax remains next to the SiC/SiO2 interface for all examined CP. Nevertheless, unlike in the ALL, the degree of current spreading in the circular and stripe designs saturates above 10μm CP, due to the newly added lateral resistance along the length of the accumulation layer. Thus, RONS eventually starts to rise with CP (due to the inefficient area consumption). More importantly, this also leads to a saturation of the local Joule heating profile and thus of Tmax (unlike in the ALL, where it falls continuously with CP).

Conclusion
In conclusion, this work has clearly demonstrated that there exists a strong correlation between the evolution of the maximum junction temperature (hotspot) and the cell layout, which is not only a function of the JFET area density but also of the current density profile and current spreading in the JFET/accumulation region. Moreover, the average local junction temperature, as well as the location of the hotspot, are both responsible for the device's thermal runaway failure mechanism.