Design of an Integrated Power Module for Silicon Carbide MOSFET with Self-Compensation of the Magnetic Field

Compactness, efficiency, and light weight are the key topics in the design of power conversion systems for transportation applications. This demand is achievable by using wide band gap devices such as SiC devices, characterized by the high switching speed and low on-resistance. However, this trend imposes new challenges and the effect of parasitic elements of power package during switching transient becomes significant. Hence, new packaging solutions should be investigated for addressing this concern. This paper presents a new multichip power module architecture, where its design considering capacitive and inductive stray elements is carried out. Using Ansys Q3D Extractor, electromagnetic simulations are achieved to extract the inductive and capacitive parasitic element of one leg of a three-phase inverter.


Introduction
The Silicon (Si) material is a semiconductor used in many power electronics applications. The latest technological developments have led to minimal dimension requirements that would be a hard physical limit for this material. Thus, the standard solution proposed to overcome these limits is to replace Si with Silicon Carbide (SiC) material [1]. In fact, SiC MOSFETs have shown several advantages over the similarly rated Si IGBTs, such as a higher switching speed and thus lower switching losses. Hence, SiC devices enable the fabrication of converter systems with high performance, high efficiency, and high power density, meeting better new market requirements [2]. However, using these SiC-based switches makes the system very sensitive to parasitic circuit elements. Also, they can lead to higher electromagnetic interferences (EMI), voltage, and current ringing during switching. For example, high di/dt in a switching cell might result in a severe turn-off overvoltage due to the presence of the parasitic stray inductance that must be minimized. Therefore, to take full advantage of the good performances of SiC devices and ensure a good operation of power converters, the optimization of their packaging technology is necessary [3].
In this paper, we propose a new design of a multichip power module, with low parasitic inductance specifications and symmetrical parasitic capacitances. The presented design is based on optimizing the placement of embedded transistors in a PCB layout which allows a self-compensation of the magnetic field that reduces the parasitic inductances of the circuit [4].

Design Principle
It is well known that a low-inductive switching loop is necessary to obtain fast switching. As well, to avoid large EMI during the switching of the transistors, a special attention to the electromagnetic compatibility (EMC) design rules are mandatory. Hence, this section presents the characteristic of the design that considers capacitive and inductive stray elements to obtain high switching speed capabilities.

Inductance of the overall current commutation loop (LCCL).
To reduce LCCL, several techniques are considered. As shown in the cross section view of Fig. 1, the power switches are integrated between two PCBs (PCB1 and PCB2) with the flip-chip technology. This technology demonstrates considerable improvements in switching performance, since it allows decreasing LCCL and improving the symmetry of common mode capacitances when compared to conventional packages [5]. Also, the flip-chip technology applied to the transistors, reduces the surface of the switching cell, and minimizes LCCL.  EMC. With short switching times, when SiC components are used, the capacitive coupling elements create a considerable impact on the conducted EMC. As shown in Fig. 3, the common mode (CM) capacitor at the output node (OUT), is due to the layout of the module, the interconnections, and the load. The high dv/dt at this node generates common mode currents through COUT. Also, the CM current is conducted by the capacitor of gate driver insulation (Ciso) that must be reduced. Although, CDC+_GND and CDC-_GND constitute a recycling path to the CM current inside the module. They can be considered as a part of the CM filter. To keep the advantage of CDC+_GND and CDC-_GND, bus voltage must be stable enough, and it is necessary to have a symmetrical layout at DC+ and DC-. Also, the (a) (b) (c)

Silicon Carbide and Related Materials 2021
symmetrization of COUT_DC+ and COUT_DC-, which are parallel to the output capacitances of HS and LS transistors respectively, is necessary to have a simultaneous switching of these transistors. Fig. 3: Representation of the parasitic capacitors.

Q3D Simulations Results
To verify the advantage of this innovative power packaging technology that combines (i) the flipchip of the MOSFETs and (ii) the diametrically opposed position (designated as configuration 1), a performance study was carried out to compare this first configuration (Fig. 4a) with two others (configuration 2 and 3). Configuration 2 presents a non-crossed position of the transistors but keeps the flip-chip technology (Fig. 4b) that should confirm the interest of the self-compensation of the magnetic field in configuration 1. Also, configuration 3 presents a classical disposition of the transistors without a flip-chip (Fig. 4c), with an architecture closer to the one of conventional packages that should demonstrate the importance of the symmetrical layout in configuration 1. Stray inductances. L1 and L2 shown in Fig. 5, represent the stray inductances, due to the packaging, of branch 1 and 2 respectively, and M12 represents the mutual inductance between these branches. The total parasitic inductance is represented by the Eq. 1: The equivalent parasitic inductance of the CCL can also be represented by the Eq. 2: The extractions of self and mutual inductances are realized with Ansys Q3D software. To illustrate the influence of the self-compensation of the magnetic flux, the inductance matrix of the first configuration is shown in Eq. 3 and compared with Eq. 4 that represents the inductance of the second configuration.
As can be seen, the mutual inductances between paralleled branches of the first configuration are negative. The equivalent parasitic inductances LCCL are 0.86nH and 1.12nH for the first and the second configuration, respectively. This proves the hypothesis of self-compensation of magnetic field, where the mutual inductances cancel 23% of the total parasitic inductance and reduces its effect. Common mode capacitors. The extractions of the common mode capacitors are also realized by Ansys Q3D extractor. The results obtained for the first configuration are now compared with the second and third configurations.  Table 1 shows that the output capacitance due to the layout design (COUT_Layout) is negligeable for the first and second configurations. Also, the capacitance comparison between CDC+_GND and CDC-_GND reveal that the layout at DC+ and DC-are more symmetric for configurations 1 and 2 due to the flip chip technology. Also, the optimization of the layout is clearly demonstrated by the similar values obtained for the capacitances between DC+, DC-and the output node (COUT_DC+ and COUT_DC-).

Summary
In this paper, the estimation of the stray inductance of a phase leg commutation loop is studied, also the common mode capacitors are considered. The above Q3D-extracted results confirm our hypothesis concerning the minimization of the parasitic inductance of the switching loops by the selfcompensation concept. To complete our study, the analysis of the proposed module should be verified by experimental studies. A double pulse test will confirm the effectiveness of mutual inductance cancellation, and an EMC test will confirm the advantages of the layout symmetrization.

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Silicon Carbide and Related Materials 2021