Materials Science Forum, ISSN: 1662-9752, Vol. 1158, pp 17-25

doi: 10.4028/p-MxQp6y

© 2025 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2024-09-04

Revised:
2025-02-12

Accepted:
2025-02-20

Online:
2025-09-08

Impact of Interfacial Layer Thickness on the Electrical Performance of /High-k Stacks on -SiC

The original version of this paper is available on https://www.scientific.net/MSF.1158.17.pdf

Sandra Krause , Aleksey Mikhaylov , Uwe Schroeder , Thomas Mikolajick , Andre Wachowiak

TU Dresden, 01062 Dresden, Germany

Infineon Technologies Austria AG, Siemensstraße 2, 9500 Villach, Austria

NaMLab gGmbH, Nöthnitzer Straße 64, 01187 Dresden, Germany

sandra.krause@mailbox.tu-dresden.de, aleksey.mikhaylov@infineon.com, uwe.schroeder@namlab.com, thomas.mikolajick@namlab.com andre.wachowiak@namlab.com

Abstract

This study investigates the role of the electrical failure of the film in the breakdown of and stacks. Our findings indicate that the breakdown is governed by the film, regardless of its thickness. This highlights the importance of carefully considering the interfacial layer when using high-k materials in SiC devices. We demonstrate that thicker layers offer several benefits, including reduced leakage, enhanced thermal stability and electrical strength, and decreased trapping. In contrast, stacks with thinner have a higher effective k value, exploiting the benefits of high-k dielectrics. Our experimental results suggest that a layer underlying 30 nm crystalline or provides optimal performance. Furthermore, we present calculations that reveal the trade-off between thickness, k value, and breakdown voltage for a 50 nm thick dielectric stack. Our results imply that a k value exceeding 20 does not yield significant benefits in 50 nm thick /dielectric stacks.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1158.17.pdf

The use of (dielectric constant ) as a gate dielectric has become a limiting factor in the development of high-performance silicon carbide ( SiC ) power devices. It is widely recognized that replacing with high-k dielctrics can overcome these limitations and offer new opportunities for device optimization [1]. However, the SiC /oxide interface poses a significant challenge. The lattice mismatch between the crystalline dielectric and the SiC substrate is a common issue for most high-k oxides [1], [2], [3]. Furthermore, the natural growth of carbon-rich on SiC during the deposition or annealing of the high-k oxide is unavoidable [4]. Both effects can lead to interface defects, which can significantly deteriorate the device performance [1], [5].

To address the challenges associated with the oxide interface, numerous studies have demonstrated the benefits of intentionally adding a high-quality interfacial film. This interlayer provides several advantages, including a low density of interface states ( ) [6], high channel mobility [7], smooth interface morphology [8], low trap density in the bulk of the film [1], [9] and low frequency dispersion [6]. Additionally, the interlayer provides a high band offset towards the conduction/valence band ( ) of SiC [3], which positively impacts the leakage current [9], [10] and flatband voltage [10]. However, the film reduces the effective k value of the stack [4], which undermines the benefits of introducing high-k dielectrics. To our knowledge, there is a lack of comprehensive studies that explore a wide range of interlayer thicknesses and consider parameters relevant to power devices. Therefore, a conclusion still needs to be drawn regarding the optimal compromise for the interfacial layer thickness. This study aims to bridge this gap by systematically investigating the implications of different thicknesses on power device performance.

Experimental

The original version of this paper is available on https://www.scientific.net/MSF.1158.17.pdf

This study investigates the behavior of MOS capacitors with high-k stacks on n-type substrates. Hafnium oxide ( ) or zirconium oxide ( ) films with a target thickness of 30 nm were deposited by atomic layer deposition (ALD) on top of films with thicknesses ranging from 2 to 45 nm (Fig. 1a). The ALD deposition was done at with as oxidant and a tris(dimethylamino)-cyclopentadienyl-Zirconium- precursor for and a tris(dimethylamino)cyclopentadienyl-hafnium- precursor for . Both and are promising materials for high-k dielectric films [1], [2], [8], [12]. The films were deposited and subsequently nitrided to ensure high quality interfaces meeting cutting-edge industry standards. A titanium nitride / titanium / platinum stack was deposited as the top electrode. Following deposition, the samples were annealed in Argon ambient at for 1 minute, resulting in crystallization of the high-k layer (Fig. 1b, c). The layer thicknesses were determined using X-ray reflectometry (XRR) and verified by transmission electron microscopy (TEM). The crystallographic phase of the high-k films was determined from the peak positions in grazing incidence X-ray diffraction measurements (GIXRD). The k value was calculated from the MOS capacitance in the accumulation regime, representing an "effective" k that accounts for the entire dielectric stack, including and the high-k layer. The k value of the high- k film was calculated using an equivalent circuit model consisting of two capacitors in series, the measured layer thicknesses, and the k value of . The leakage current density and the electric breakdown field were determined using current-voltage (IV) measurements. A positive voltage was applied to the top electrode to induce accumulation in the metal / insulator / SiC structure. The was defined at a of .

Fig. 1. (a) Schematic representation of the investigated samples. TEM image of a sample with (b) and ca. and (c) ca. and ca. , revealing the lattice planes of the crystal grains.

Fig. 1. (a) Schematic representation of the investigated samples. TEM image of a sample with (b) and ca. and (c) ca. and ca. , revealing the lattice planes of the crystal grains.

Results

The original version of this paper is available on https://www.scientific.net/MSF.1158.17.pdf

Stacked capacitors with thicker layers demonstrate a higher and lower k (Fig. 2a), which is attributed to the higher breakdown strength and lower k of . In contrast, capacitors with pure follow the opposite trend because thinner oxide films generally exhibit a higher . The latter was measured on reference capacitors with film only and aligns well with literature values (Fig. 2a) [13]. For the samples with thin layers, the stacks exhibit a higher than the samples. This can be explained by the more suitable band alignment for on SiC [1]: although and have a similar bandgap of 5.7 eV and 5.6 eV , respectively, the conduction band offset between and SiC is 1.8 eV , which is larger than between and . However, for the samples with thicker , the physical distance between the semiconductor and the high-k oxide reduces this effect. As a result, the breakdown of the plays a more significant role: the higher k value of the tetragonal crystalline , [8] compared to the monoclinic crystalline leads to a higher electric field within the film at the same applied voltage. Consequently, the critical breakdown field within the film is reached at lower voltages for the stacks, resulting in a lower .

The breakdown of the film plays a crucial role in the breakdown behavior of the dielectric stack, as illustrated in Figure 2b: the IV curves reach the breakdown condition when the electric field within the film ( ) reaches the breakdown values presented in Fig. 2a [13]. This observation leads to the conclusion that the breakdown governs the breakdown of the stacked dielectric film. A slight deviation towards higher fields can be attributed to the omission of the contribution of the surface potential [15] and the shift in (cf. Fig. 4). EsiO2 was calculated using eq. (7) in [15]

with as the applied voltage, , and the determined from capacitance-voltage measurements.

Fig. 2. (a) Electric breakdown field of and stacks of and high-k dielectric. (b) of the and stacks versus the electric field within the film.

Fig. 2. (a) Electric breakdown field of and stacks of and high-k dielectric. (b) of the and stacks versus the electric field within the film.

The exact breakdown mechanism has been described in detail by Kumta et al. [16]. Our samples exhibit a similar behavior: after the film breakdown, the entire applied voltage drops across the remaining high-k layer. For stacks with thick films, this leads to an immediate breakdown of the stack (1-step breakdown). In contrast, samples with thin reach the breakdown limit in at lower applied voltages. The high-k oxide remains intact, exhibiting a high leakage current, and breaks down subsequently ( 2 -step breakdown). This phenomenon was validated by measuring a monitor current during the dielectric relaxation of the internal polarization within the high-k dielectric [16], i.e., at 0 V applied. The procedure is illustrated in the inset of Fig. 3a. When the externally applied field is removed, a decaying current in the opposite direction to the leakage current can be measured. This relaxation current ( ) stems from free hopping charges that neutralize the internal bound charges that previously caused the polarization of the dielectric. Notably, is negligible for but can be detected in and until the dielectric undergoes a breakdown [16]. The leakage curve and the corresponding monitor current in Fig.3a clearly demonstrate the 2-step breakdown of the stack with and .

For a more comprehensive understanding of the breakdown phenomena of the stacks, I-V measurements were carried out at elevated temperatures (exemplary data for stacks shown in Fig. 3b). For the stacks with thin film, the primary conduction mechanism is trap-assisted tunneling with a significant temperature dependence [17]. At , the is reduced by compared to the measurements at , and the at is increased by four orders of magnitude. For the sample with , Fowler-Nordheim tunneling is the predominant mechanism, which shows much less temperature dependence [17]. For measurements performed at , at remains within the detection limit, and is reduced by only as
compared to measurements at . The reduction of can be attributed to the temperaturedependent Fermi-Dirac distribution of the electrons, which translates to an increased availability of electrons for tunneling at higher temperatures.

Fig. 3. (a) Leakage and relaxation current in the stack of and . The relaxation current was measured after a 1 s delay time. The inset displays the presence of the relaxation current over time. (b) J-E plot for the sample with and measured at temperatures between and .

Fig. 3. (a) Leakage and relaxation current in the stack of and . The relaxation current was measured after a 1 s delay time. The inset displays the presence of the relaxation current over time. (b) J-E plot for the sample with and measured at temperatures between and .

Fig. 4. (a) Consecutive CV measurements of the sample with with . (b) Several CV measurements with different sweep delays, i.e., the time intervals between voltage application and capacitance measurement ( with ). (c) Hysteresis of the first CV sweep for samples with 2 and , depending on the maximum applied bias.

Fig. 4. (a) Consecutive CV measurements of the sample with with . (b) Several CV measurements with different sweep delays, i.e., the time intervals between voltage application and capacitance measurement ( with ). (c) Hysteresis of the first CV sweep for samples with 2 and , depending on the maximum applied bias.

CV measurements were performed to determine the k -value and trapping behavior of the stacks. Stacks with thin exhibit a significant hysteresis between the up-sweep and down-sweep curves (Fig. 4), indicating that electrons from the SiC accumulation layer are trapped at the high-k interface or within the high-k [5]. With every subsequent measurement, the CV curve shifts towards higher voltages, resulting in a higher and smaller hysteresis (Fig. 4a). This implies that trapped electrons are not released during the down-sweep [18]. The shift saturates after a certain number of measurements, indicating that all accessible traps are filled after a specific time.

The hysteresis is found to increase under two conditions i) when the sweep delay of the measurement is increased (Fig. 4b), and ii) when the maximum applied bias is increased (Fig. 4c). The sweep delay refers to the time interval between applying the bias and measuring the corresponding capacitance. At slower sweep rates, the electrons have more time to fill so-called "slow" traps. At higher maximum bias, the electrons possess more energy and can access traps, which are energetically not accessible at lower fields. Both effects lead to an increase in the number of trapped charges, resulting in a larger hysteresis.

The shift of was evaluated over several measurement runs in Fig. 5a. The figure shows the saturation effect mentioned earlier and the difference in behavior for different thicknesses. Notably, the charge trapping is more pronounced in films with thin . In contrast, a thicker film acts as both a physical and an electrical barrier, inhibiting electrons from tunneling towards the high-k oxide [4]. Fig. 5b shows the decline of the hysteresis for thicker films. The hysteresis was measured during the first measurement run. The maximum applied voltage was adjusted to ensure the same field ( ) for all samples, i.e., 8 V for the sample with and 20 V for the sample with . Fig. 5c shows the decline of the , measured at the first up-sweep, for samples with thicker . The ideal , i.e., in complete absence of any trapped, fixed, or mobile charges within the dielectric, depends only on the work function of the electrode metal and the electron affinity of the semiconductor. In our case, for SiC and TiN, it has a value of 1.0 V [19]. Predominantly, the trapped and fixed charges located in the oxide and at the interfaces shift Vfb. Negative charges trapped in the dielectric shift towards higher positive voltages. With thicker interfacial , the trapped charges within the high-k material are further away from the SiC surface which weakens their influence on the voltage shift [5]. Moreover, the shift of towards negative values is associated with an accumulation of positive charges within the [11]. The more negative VFB with thicker could be explained by positive fixed charges in the . The difference between the and series indicates a corresponding difference in fixed charges within the bulk of the high-k or at the high-k/ interface.

Fig. 5. (a) Flatband voltage of consecutive CV runs. (b) CV hysteresis versus thickness. (c) of the first up-sweep in CV measurements versus the thickness of the sample. For all measurements, the maximum applied bias was , i.e., the maximum voltage was adjusted according to the stack thickness.

Fig. 5. (a) Flatband voltage of consecutive CV runs. (b) CV hysteresis versus thickness. (c) of the first up-sweep in CV measurements versus the thickness of the sample. For all measurements, the maximum applied bias was , i.e., the maximum voltage was adjusted according to the stack thickness.

These results highlight the importance of carefully designing the thickness ratio of the and high-k films for a particular application. Therefore, field calculations are presented in Fig. 6. A stack with a total thickness of 50 nm , consisting of a film and a high-k film, was assumed. The thickness of the layer varied from 0 to 50 nm , resulting in the fraction in the stack ranging from to . The k value of the high- k material was varied from 0 to 40 . The electric fields within the two dielectric films at a specific applied voltage were calculated by using eq. (1). The breakdown condition of the stack is reached when the field within the film surpasses the breakdown limit of as presented in [13] and confirmed in Fig. 2a. In both plots, Fig. 6a and b, the curves resemble the breakdown condition for the film, i.e., the voltage at which the field within the film exceeds the breakdown limit. Several effects determine the shape of the curves in both plots: i) a high k value of the high- k oxide, i.e., a strong polarization, pushes the electric field towards the , ii) for a given k value and applied voltage, the electric field in the is lower for a thicker film than for a thin film, iii) thinner films exhibit a higher breakdown field. The last two effects are contrary and lead to the crossing of the curves in Fig. 6a. In this plot, each line shows the expected breakdown voltage for a particular stack combination. The crossing occurs at a range of
k values between 12 and 20 , revealing that in that range, the variation of thickness between 2 and 10 nm has only a small influence on the breakdown voltage. Hence, the favored thickness is as small as possible to maintain a high effective k value. At higher k values, the polarization of the high-k material is so strong that the electric field reached within the film is exceedingly high. Therefore, the ESiO2 must be reduced by increasing the film thickness.

Fig. 6b provides further guidance for the stack composition: To withstand a specified voltage, the stack must be designed in such a way that the combination of its thickness and k value lies above the curve. The area below the curve represents all stack combinations where the electric field within the exceeds the breakdown limit. The background of the graph area visualizes the overall k value of the specific stack combination calculated from the thicknesses and k values by using

Both plots suggest that using high-k materials with in a stack with is not beneficial. This is because either the breakdown voltage is very low or the thickness has to be increased significantly. This, in turn, reduces the effective k value of the stack ( ), which negates the effort of increasing the k value of the oxide stack.

Fig. 6. Theoretical field calculation for capacitors with high-k oxide stacks with as the film thickness, as the k value of the high-k oxide, and as the voltage applied to the entire stack, and flatband voltage . The total stack thickness is constant at 50 nm . (a) The curves represent the breakdown voltage for a stack consisting of a film with the specified thickness and a high- k dielectric with the specified k value. (b) The background color displays the effective k value of the stack. The curves represent the breakdown condition of the film: in stacks that appear below the curve the at the specified voltage is higher than the breakdown field of resulting in a breakdown of the stack.

Fig. 6. Theoretical field calculation for capacitors with high-k oxide stacks with as the film thickness, as the k value of the high-k oxide, and as the voltage applied to the entire stack, and flatband voltage . The total stack thickness is constant at 50 nm . (a) The curves represent the breakdown voltage for a stack consisting of a film with the specified thickness and a high- k dielectric with the specified k value. (b) The background color displays the effective k value of the stack. The curves represent the breakdown condition of the film: in stacks that appear below the curve the at the specified voltage is higher than the breakdown field of resulting in a breakdown of the stack.

Discussion

The original version of this paper is available on https://www.scientific.net/MSF.1158.17.pdf

This study demonstrates that in and stacks, the film breaks down first, independent of its thickness. The electrical failure of the film leads to a significant increase in the leakage current and, ultimately, to the breakdown of the stack. With thicker , the FowlerNordheim mechanism dominates the carrier conduction, enabling low leakage and high breakdown field at . However, thick significantly reduces the effective k value of the stack. For a final decision about the most suitable trade-off, Fig. 7 compares the relevant parameters for all the investigated thicknesses. The samples with 7 nm (green area) provide the best compromise between all parameters, including a comparatively high k value. Therefore, we conclude that 7 nm of interfacial below 30 nm of crystalline or offers the best trade-off. For these stacks, the dielectric constant remains high, at 13 for the stack and 11 for the stack. The hysteresis at an applied bias of is reduced by for the and for the samples compared to the stack with 2 nm . The average breakdown fields of the entire stack are and , respectively, which is reasonably high. The leakage current density at for the stacks is and for the stacks. This is well below the leakage limit of widely accepted in literature [20].

Fig. 7. Comparison of (a) and (b) samples with all 5 investigated thickness values. For clarity, the graph axes are defined such that the least favorable values are centralized. The desired metrics, e.g., high EBD and low Jleak, are furthest away from the center. Consequently, a larger area encompassed by a sample indicates a more suitable performance.

Fig. 7. Comparison of (a) and (b) samples with all 5 investigated thickness values. For clarity, the graph axes are defined such that the least favorable values are centralized. The desired metrics, e.g., high EBD and low Jleak, are furthest away from the center. Consequently, a larger area encompassed by a sample indicates a more suitable performance.

Conclusion

The original version of this paper is available on https://www.scientific.net/MSF.1158.17.pdf

The results highlight the importance of thoughtfully designing the thickness ratios of the and high-k films in dielectric stacks. Theoretical calculations of the electric fields in a 50 nm stack indicate that the k value of the high- k material should be lower than 20 to avoid early breakdown due to breakdown.

Acknowledgments

The original version of this paper is available on https://www.scientific.net/MSF.1158.17.pdf

This work was co-financed by the European Union and from tax revenues on the basis of the budget adopted by the Saxon State Parliament.

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The original version of this paper is available on https://www.scientific.net/MSF.1158.17.pdf

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