Materials Science Forum, ISSN: 1662-9752, Vol. 1159, pp 67-72

doi: 10.4028/p-xm5gzM

© 2025 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2024-09-20

Revised:
2025-02-12

Accepted:
2025-03-10

Online:
2025-09-09

Fabrication of the Planar SiC Gate-all-Around JFET with Channel Dose Modulation

The original version of this paper is available on https://www.scientific.net/MSF.1159.67.pdf

Takanori Amamiya , Masayuki Yamamoto , Hitoshi Umezawa , Koji Nakayama , Takeharu Kuroiwa , Shin-Ichiro Kuroki , Yasunori Tanaka

Advanced Power Electronics Research Center (ADPERC), AIST, Japan

Department of Electrical and Electronic Engineering, University of Yamanashi, Japan

Research Institute for Semiconductor Engineering, Hiroshima University, Japan

at.amamiya@aist.go.jp, byamamoto.masayuki@aist.go.jp, chitoshi.umezawa@aist.go.jp

koji.nakayama@aist.go.jp, kuroiwa.takeharu@aist.go.jp, skuroki@hiroshima-u.ac.jp, yasunori-tanaka@aist.go.jp

Keywords: Silicon Carbide (SiC), Gate-all-around (GAA), JFET, common-source amplifier, harsh environment

Abstract

Currently, silicon carbide ( SiC ) is widely recognized as a wide bandgap semiconductor, with expanding applications in harsh environments, such as high temperature and radiation exposure. In this study, we fabricated a planar structure gate-all-around junction field-effect transistor (JFET), wherein the channel region is formed through ion implantation at varying doses. We successfully produced both normally-on and normally-off JFETs. Moreover, we constructed a JFET common source amplifier. The amplifiers achieved a maximum gain of -226.7 ( 47.1 dB ) at a supply voltage of .

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1159.67.pdf

At present, siliocon carbide ( SiC ) is known as a leading wide bandgap semiconductor material because of its high tolerance to harsh environments, such as high temperature and radiation [1]. Realizing SiC integrated circuits (ICs), such as operational amplifiers, will enable devices based on SiC ICs to operate in harsh environments. Currently, four types of SiC transistors are mainly studied: bipolar junction transistors (BJTs), junction field-effect transistors (JFETs), metal-oxidesemiconductor field-effect transistors (MOSFETs), and metal-semiconductor field-effect transistors (MESFETs) [2-10]. The advantage of SiC JFETs is that they have no gate oxide layer. It has been reported that gate oxide layers can be easily degraded by radiation [11]; therefore, SiC JFETs are preferable to SiC MOSFETs in radiation environments. Meanwhile, SiC MESFETs have an inadequate interface contact between the N-channel and P-type buried back gate layer, which causes backgating [10]. For these reasons, SiC JFETs are likely the prime choice for SiC ICs operating in harsh environments. Recently, not only n-type but also p-type SiC JFETs have been demonstrated [12].

Increasing channel density is beneficial for enhancing device performance [13]. However, it raises the pinch-off voltage, leading to higher power consumption in ICs due to the need for elevated supply voltages. Therefore, to fabricate the gate region, double-gate and gate-all-around (GAA) structures are preferable to single-gate structures because a lower pinch-off voltage is suitable for the same channel density. Recently, we developed a SiC JFET featuring a GAA design, which theoretically optimizes transconductance [14]. In the design, fabricating the bottom layer required extremely high-energy ion implantation, such as 3 MeV , and oblique ion implantation after gate trench etching, making unconventional processes significantly challenging.

To overcome these challenges, we propose and evaluate the characteristics of a JFET with a new planar GAA structure. In this design, the gate region is fabricated by ion implantation at varying doses without the need for such high-energy implantation. In addition, two types of JFETs, normally- on and normally-off JFETs, can be customized by varying the dose amount. Further, we
constructed a common-source amplifier as a simple electronic circuit using the JFETs and assessed the maximum voltage gain.

Fig. 1. (a) Top and (b) cross-sectional schematics of the planar n-type SiC GAA JFET. Five n-type channel stripes (orange) are embedded beneath the source/drain (dark orange) and gate top (blue) regions in the n - epitaxial layer (light yellow). The gate length and width are and , respectively. The device is isolated by trenches around it.

Fig. 1. (a) Top and (b) cross-sectional schematics of the planar n-type SiC GAA JFET. Five n-type channel stripes (orange) are embedded beneath the source/drain (dark orange) and gate top (blue) regions in the n - epitaxial layer (light yellow). The gate length and width are and , respectively. The device is isolated by trenches around it.

Device Fabrication

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Fig.1(a) and (b) show the top and cross-sectional schematics of the proposed JFET, respectively. Five n -type channel stripes are embedded beneath the source/drain and gate top regions in the n - epitaxial layer. The n-type channels (width: ) are separated by the gate side region ( ). The gate length and width are and , respectively. The margin between the p+ gate and source/drain regions is , and the width of the contact holes is . The device is isolated by trenches (width: , depth: ) around it.

First, the gate bottom region is firstly formed by Al-ion implantation into the entire epitaxial layer ( ) grown on a -SiC wafer. The n -type channels, source/drain, gate side, gate top regions are then formed. We use six channel doses ( , 1.4, 1.6, and ) to control the gate threshold voltage. When the channel dose is , the target channel density is approximately .

After device isolation by SiC trench etching, we performed activation annealing , 10 min .). Ni contact metal is deposited on both sides of the wafer and sintered at 500 . The device fabrication is completed by attaching a thick Al electrode on the surface side while the back side is covered with Ti, Ni, and Au layers.

IV-Characteristics of JFET

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We fabricated two types of JFETs: normally-on and normally-off JFETs, by varying the channel dose amount. These are fabricated on two wafers, named 10 SY and 11 SY . For 10SY, three channel doses , and , were selected to achieve normally-off operation; meanwhile, for 11SY, , and were chosen to achieve normally-on operation. The device characteristics were measured with Semiconductor Parameter Analyzer Agilent 4156C. Fig. 2 shows an optical microscope image of an actual GAA JFET being measured using a manual prober. The substrate is connected to GND. The transfer and output characteristics were measured for the six doses. For the transfer characteristics, was set to 10 V and was swept from -7.5 to 2.5 while measuring . For the output characteristics, for each dose, was varied from 0 to 2 V for normally-off and from -3 to 2 V for normally-on in steps of 1 V while was swept from 0 to 20 to measure .

Fig. 2. Optical microscope of actual SiC GAA JFETs.

Fig. 2. Optical microscope of actual SiC GAA JFETs.

Fig. 3 illustrates the characteristics of JFETs. Fig. 3 (a) shows the transfer characteristics of JFETs with different channel doses, indicating a shift in the gate-threshold voltage from 2.11 to - 3.76 V as the channel dose increases from to , and Fig. 3 (b) shows the logarithmic plot of the transfer characteristics of JFETs with different channel doses. As the channel dose amounts increases, the threshold voltage shifts toward negative values.

Figs. 3 (c) and (d) display the output characteristics of the normally-off JFET with a channel dose of and the normally-on JFET with a channel dose of , where the drain current in the saturation region remains nearly constant across the drain-source voltage . The device parameters are listed in Table 1. The drain current was measured for the normally-off and normally-on JFETs when and , respectively. and are calculated when and

Large-Signal Behaviors of JFET Common-Source Amplifier and Source Follower

The original version of this paper is available on https://www.scientific.net/MSF.1159.67.pdf

To test the fabricated JFETs, simple circuits - a common-source amplifier and a sourcefollower amplifier - were constructed and tested. The circuit diagrams are shown in Fig. 4 (a) and Fig. 5 (a). Fig. 4 (a) is a common-source amplifier and Fig. 5 (a) is a source-follower circuit. This measurement is also conducted using Semiconductor Parameter Analyzer Agilent 4156C. In the measurement of the common-source amplifier, was set to 10,20 , and 30 V with swept from -2 to 2 V while the corresponding output was measured. Similarly, for the source-follower amplifier, was swept from -2 V to the maximum under the same settings while the output was recorded.

Fig. 4 (b) shows the output voltage of the common-source amplifier under large-signal analysis. As verified in the figure, turns off when reaches 0 V , as expected. The maximum gain of the amplifier around was calculated, resulting in values of , and for , and 30 V , respectively. The gain can be determined using , calculated from the slope of the I/O characteristics. In Fig. 5 (b), the output voltage Vout of the source-follower amplifier is shown. The circuit's correct operation is confirmed by the manner the output rises in response to the input, effectively following it.

Fig. 3. (a) Transfer characteristics of normally-on and normally-off JFETs per channel dose when . (b) Logarithmic plot of transfer characteristics of normally-on and normally-off JFETs per channel dose amounts when . The color legend is the same as in (a). (c) Output characteristics of normally-off JFET for gate-source voltages ( ) of 0,1 , and 2 V . The channel dose is . (d) Output characteristics of normally-on JFET for gate-source voltage steps from -3 V to 2 V in increments of 1 V . The channel dose is .

Fig. 3. (a) Transfer characteristics of normally-on and normally-off JFETs per channel dose when . (b) Logarithmic plot of transfer characteristics of normally-on and normally-off JFETs per channel dose amounts when . The color legend is the same as in (a). (c) Output characteristics of normally-off JFET for gate-source voltages ( ) of 0,1 , and 2 V . The channel dose is . (d) Output characteristics of normally-on JFET for gate-source voltage steps from -3 V to 2 V in increments of 1 V . The channel dose is .

Summary

The original version of this paper is available on https://www.scientific.net/MSF.1159.67.pdf

In this study, normally-on and normally-off JFETs with a planar GAA structure were fabricated and demonstrated. By varying the channel dose, we successfully produced both types of JFETs. Their characteristics were measured using the Semiconductor Parameter Analyzer Agilent 4156C. In addition, simple electronic circuits, including a common-source amplifier and a source-follower amplifier, were constructed and tested using the JFETs. The maximum gains of the amplifiers near was found to be , and for , and 30 V , respectively.

Table 1. Device parameters per varied dose.

Dose [cm⁻²] | ID [μA] | r₀ [MΩ] | gm [μS] | Av = r₀gm
1.0 × 10¹³ | 1.98 | 110 | 6.10 | 671
1.2 × 10¹³ | 10.0 | 23.8 | 14.8 | 352
1.4 × 10¹³ | 2.78 | 192 | 6.06 | 1164
1.6 × 10¹³ | 16.1 | 22.5 | 17.1 | 385
1.8 × 10¹³ | 45.0 | 6.79 | 29.6 | 201

Fig. 4. (a) Common-source amplifier circuit diagram and (b) transfer characteristics of the common source amplifier. In the circuits, normally-on JFET devices are used, where the typical resistor is replaced by shorting the JFET's source and gate. The maximum gain around was observed at , and 30 V .

Fig. 4. (a) Common-source amplifier circuit diagram and (b) transfer characteristics of the common source amplifier. In the circuits, normally-on JFET devices are used, where the typical resistor is replaced by shorting the JFET's source and gate. The maximum gain around was observed at , and 30 V .

Fig. 5. (a) Source-follower amplifier diagram and (b) transfer charactristics of the source-follower amplifier circuit.

Fig. 5. (a) Source-follower amplifier diagram and (b) transfer charactristics of the source-follower amplifier circuit.

Acknowledgements

The original version of this paper is available on https://www.scientific.net/MSF.1159.67.pdf

This work was partially supported by MEXT Initiative to Establish Next-generation Novel Integrated Circuits Centers (X-NICS) Grant Number JPJ011438, the commissioned research fund provided by F-REI, and JSPS KAKENHI (S), Grant Number JP24H00035.

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The original version of this paper is available on https://www.scientific.net/MSF.1159.67.pdf

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