Challenge to 200 mm 3C-SiC Wafers Using SOI


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200 mm wafer with 3C-SiC/SiO2/Si structure has been fabricated using 200 mm siliconon- insulator (SOI) wafer. A top Si layer of 200 mm SOI wafer was thinned down to approximately 5 nm by sacrificial oxidization, and the ultrathin top Si layer was metamorphosed into a 3C-SiC seed layer using a carbonization process. Afterward, an epitaxial SiC layer was grown on the SiC seed layer with ultra-high vacuum chemical vapor deposition. A cross-section transmission electron microscope indicated that a 3C-SiC seed layer was formed directly on the buried oxide layer of 200 mm wafer. The epitaxial SiC layer with an average thickness of approximately 100 nm on the seed was recognized over the entire region of the wafer, although thickness uniformity of the epitaxial SiC layer was not as good as that of SiC seed layer. A transmission electron diffraction image of the epitaxial SiC layer showed a monocrystalline 3C-SiC(100) layer with good crystallinity. These results indicate that our method enables to realize 200 mm SiC wafers.



Materials Science Forum (Volumes 483-485)

Edited by:

Dr. Roberta Nipoti, Antonella Poggi and Andrea Scorzoni




M. Nakao et al., "Challenge to 200 mm 3C-SiC Wafers Using SOI", Materials Science Forum, Vols. 483-485, pp. 205-208, 2005

Online since:

May 2005




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