P-Type SiC Layers Formed by VLS Induced Selective Epitaxial Growth

Abstract:

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Al-Si patterns were formed on n-type 4H-SiC substrate by a photolithographic process including wet Al etching and Si/SiC reactive ion etching (RIE) process. RF 1000°C annealing under C3H8 flow was performed to obtain p+ SiC layers by a Vapour-Liquid-Solid (VLS) process. This method enables to grow layers with different width (up to 800 µm) and various shapes. Nevertheless the remaining Al-based droplets on the largest patterns are indicators of crack defects, going through the p+ layer down to the substrate. SIMS analyses have shown an Al profile with high doping concentration near the surface, high N compensation and Si/C stoechiometry variation between the substrate and the VLS layer. The hydrogen profile follows the Al profile in the VLS layer with an overshoot at the VLS/substrate interface. I-V measurements performed directly on the semiconductor layers have confirmed the formed p-n junction and allowed to measure a sheet resistance of 5.5 kW/ı

Info:

Periodical:

Materials Science Forum (Volumes 483-485)

Edited by:

Roberta Nipoti, Antonella Poggi and Andrea Scorzoni

Pages:

633-636

DOI:

10.4028/www.scientific.net/MSF.483-485.633

Citation:

M. Lazar et al., "P-Type SiC Layers Formed by VLS Induced Selective Epitaxial Growth", Materials Science Forum, Vols. 483-485, pp. 633-636, 2005

Online since:

May 2005

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$35.00

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