A Fundamental Modeling Approach for Nano-Grinding of Silicon Wafers


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The advantages of ductile regime grinding of silicon wafer such as smooth surface roughness (Ra < 10 nm) and minimum subsurface damage layer (< 10μm) have great impact on the production process of wafer. With ductile regime grinding, the subsequent processes such as etching and rough polishing processes can be minimized. To achieve ductile regime grinding, a fundamental concept is the application of grain depth of cut being less than the critical cut depth, dc, of the silicon wafer. However, dc is dependent on material properties, cutting conditions, and crystallographic orientation [1].The objective of this paper is to derive, and to investigate by experiment, the dc value for silicon wafer grinding. Following these key steps, the effects of dc on various major grinding parameters are studied.



Materials Science Forum (Volumes 505-507)

Edited by:

Wunyuh Jywe, Chieh-Li Chen, Kuang-Chao Fan, R.F. Fung, S.G. Hanson,Wen-Hsiang Hsieh, Chaug-Liang Hsu, You-Min Huang, Yunn-Lin Hwang, Gerd Jäger, Y.R. Jeng, Wenlung Li, Yunn-Shiuan Liao, Chien-Chang Lin, Zong-Ching Lin, Cheng-Kuo Sung and Ching-Huan Tzeng




H. T. Young et al., "A Fundamental Modeling Approach for Nano-Grinding of Silicon Wafers", Materials Science Forum, Vols. 505-507, pp. 253-258, 2006

Online since:

January 2006




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