Process Optimisation for <11-20> 4H-SiC MOSFET Applications

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We report on 4H-SiC MOSFET devices implemented on p-type <11-20>-oriented epitaxial layers, using a two-step procedure for gate oxide formation. First is a thin, dry, thermal SiO2 layer grown at 1050°C for 1 hour. Next, is a thick (50 nm) layer of complementary oxide deposited by PECVD using TEOS as gas precursor. With respect to the standard thermal oxidation process, this results in much improvement of the field effect mobility. For the best samples, we find a peak value in the range of 330 cm2/Vs while, on the full wafer, an average mobility of about 160 cm2/Vs is found. Up to now, this is one of the best results ever reported for 4H-SiC MOSFETs.

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Periodical:

Materials Science Forum (Volumes 527-529)

Edited by:

Robert P. Devaty, David J. Larkin and Stephen E. Saddow

Pages:

1051-1054

Citation:

C. Blanc et al., "Process Optimisation for <11-20> 4H-SiC MOSFET Applications", Materials Science Forum, Vols. 527-529, pp. 1051-1054, 2006

Online since:

October 2006

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$38.00

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