Development of 8 mΩ-cm2, 1.8 kV 4H-SiC DMOSFETs
8 mΩ-cm2, 1.8 kV power DMOSFETs in 4H-SiC are presented in this paper. A 0.5 μm long MOS gate length was used to minimize the MOS channel resistance. The DMOSFETs were able to block 1.8 kV with the gate shorted to the source. At room temperature, a specific onresistance of 8 mΩ-cm2 was measured with a gate bias of 15 V. At 150 oC, the specific onresistance increased to 9.6 mΩ-cm2. The increase in drift layer resistance due to a decrease in bulk electron mobility was partly cancelled out by the negative shift in MOS threshold voltage at elevated temperatures. The device demonstrated extremely fast, low loss switching characteristics. A significant improvement in converter efficiency was observed when the 4H-SiC DMOSFET was used instead of an 800 V silicon superjunction MOSFET in a simple boost converter configuration.
Robert P. Devaty, David J. Larkin and Stephen E. Saddow
S. H. Ryu et al., "Development of 8 mΩ-cm2, 1.8 kV 4H-SiC DMOSFETs", Materials Science Forum, Vols. 527-529, pp. 1261-1264, 2006