With a simple processing sequence using only patterned aluminum (Al), dislocations and stacking faults were examined in thick n- epitaxial layers including a grown p+ layer on top. The thicknesses of the n- layers were 100 and 150 μm, values that are typical for fabricating 10 kV PiN diodes. High temperature sintering of the metal film was avoided making this a potentially nondestructive scheme for evaluating SiC epitaxy. Faulting of basal plane dislocations (BPDs) and the resulting forward voltage, Vf, increase were examined at current densities up to 20 A/cm2. A simple guard ring structure defined in the Al pattern was successfully used to confine the current through the epitaxial layers to the area inside of the ring. Kelvin contacts compensated for voltage drops at the Al/SiC interfaces. As a result, current-voltage characteristics and electroluminescent imaging were obtained across a known area of the PiN layer at currents densities ranging from 20 A/cm2 to 7 × 10-3 A/cm2.