Impact of Annealing Temperature Ramps on the Electrical Activation of N+ and P+ Co-Implanted SiC Layers

Abstract:

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We have performed nitrogen and phosphorus co-implants at room temperature to obtain high n-type carrier concentration layers in SiC. An inductive heating RTA furnace has been used for the activation annealing. The influence of the temperature ramp parameters such as rise/decrease temperature speed and intermediate annealing steps on the dopant activation rate and surface morphology have been investigated. A reduction of the temperature ramp slope reduces the surface roughness by 50%. Inclusion of a pre-activation annealing step at low temperatures (1300°C) further reduces the surface roughness. However, the use of slower ramps or an intermediate annealing step during ramp up reduces the free carrier concentration. The faster the ramp up, the higher the activation rate and the resulting doping. We also demonstrate that the inclusion of a postactivation annealing at intermediate temperatures (1150°C) reduces significantly the surface roughness. In addition, the use of this post-annealing treatment does not degrade the activation rate nor the carrier Hall mobility, and activation rates close to 100% have been obtained.

Info:

Periodical:

Materials Science Forum (Volumes 527-529)

Edited by:

Robert P. Devaty, David J. Larkin and Stephen E. Saddow

Pages:

795-798

DOI:

10.4028/www.scientific.net/MSF.527-529.795

Citation:

S. Blanqué et al., "Impact of Annealing Temperature Ramps on the Electrical Activation of N+ and P+ Co-Implanted SiC Layers", Materials Science Forum, Vols. 527-529, pp. 795-798, 2006

Online since:

October 2006

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$35.00

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