Correlation between Current Transport and Defects in n+/p 6H-SiC Diodes
This paper reports on the defects created in a 6H-SiC p-type substrate by a process of ion implantation and a quite low temperature annealing (1300 °C), suitable for the realization of the source/drain regions of a MOSFET because it does not give rise to step bunching phenomena. Current voltage measurements showed the presence of a group of diodes featured by excess current. The effects of defects under the implanted layer on the transport properties of the diodes were investigated by DLTS: four hole traps were detected in all the measured diodes; besides, a broadened peak around 550 K was detected in the diodes that show excess current.
Robert P. Devaty, David J. Larkin and Stephen E. Saddow
M. Canino et al., "Correlation between Current Transport and Defects in n+/p 6H-SiC Diodes", Materials Science Forum, Vols. 527-529, pp. 811-814, 2006