A Comparison of High Temperature Performance of SiC DMOSFETs and JFETs


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High temperature characteristics of 4H-SiC power JFETs and DMOSFETs are presented in this paper. Both devices are based on pn junctions in 4H-SiC, and are capable of 300oC operation. The 4H-SiC JFET showed very predictable, well understood temperature dependent characteristics, because the current conduction depends on the drift of electrons in the bulk region, which is not restricted by traps in the MOS interface or at the pn junctions. On the other hand, in a 4H-SiC DMOSFET, electrons must flow through the MOS inversion layer with a very high interface state density. At high temperatures, the transconductance of the device improves and threshold voltage shifts negative because less electrons are trapped in the interface states, resulting in a much lower MOS channel resistance. This cancels out the increase in drift layer resistance, and as a result, a temperature insensitive on-resistance can be demonstrated. The performance of the two devices are compared, and a discussion of issues for their high temperature application is presented.



Materials Science Forum (Volumes 556-557)

Edited by:

N. Wright, C.M. Johnson, K. Vassilevski, I. Nikitina and A. Horsfall




S. H. Ryu et al., "A Comparison of High Temperature Performance of SiC DMOSFETs and JFETs", Materials Science Forum, Vols. 556-557, pp. 775-778, 2007

Online since:

September 2007




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[3] S. Ryu et al.: presented at HiTEC, May 15 - 18, 2006, Santa Fe, NM.

[4] A. Agarwal et al.: Silicon Carbide, Recent Major Advances, Springer-Verlag Berlin Heidelberg 2004, Germany, p.785.

100 200 300 400 500 600.

[10] -7.

[10] -6.

[10] -5.

[10] -4.

[10] -3.

[10] -2.

[10] -1 VGS = 0V ID (A) VDS (V) RT.

[50] o C 100 o C 150 o C 200 o C 250 o C 300 o C.

100 200 300 400 500 600.

[10] -8.

[10] -7.

[10] -6.

[10] -5.

[10] -4.

[10] -3.

[10] -2.

[10] -1 VDS (V) VGS = -33 V @ RT @ 50.

C @ 100.

C @ 150.

C @ 200.

C @ 250.

C @ 300.

C ID (A) (a) (b) Fig. 6. Blocking characteristics of (a) the 4H-SiC JFET and (b) the 4H-SiC DMOSFET. A maximum drain bias of 600 V was used, and a VGS of -33 V was used for the JFET and a VGS of 0 V was used for the DMOSFET.

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