Challenges for Improving the Crystal Quality of 3C-SiC Verified with MOSFET Performance
In 3C-SiC MOSFETs, planar defects like anti-phase boundaries (APBs) and stacking-faults (SFs) reduce the breakdown voltage and induce leakage current. Although the planar defect density can be reduced by growing 3C-SiC on undulant-Si substrate, specific type of SFs, which expose the Si-face, remains on the (001) surface. Those SFs increase the leakage current in devices made with 3C-SiC. In order to eliminate the residual SFs, an advanced SF reduction method involving polarity conversion and homo-epitaxial growth was developed. This method is called switch-back epitaxy (SBE) and consists of the conversion of the SF surface polarity from Si-face to C-face and following homo-epitaxial growth. The reduction of the SF density in SBE 3C-SiC results in a tremendous improvement of the device performance. The combination of the achieved blocking voltage with the demonstrated high current capability indicates the potential of 3C-SiC vertical MOSFETs for high and medium power electronic applications such as electric and hybrid electric vehicle (EV/HEV) motor drives.
Akira Suzuki, Hajime Okumura, Tsunenobu Kimoto, Takashi Fuyuki, Kenji Fukuda and Shin-ichi Nishizawa
H. Nagasawa et al., "Challenges for Improving the Crystal Quality of 3C-SiC Verified with MOSFET Performance", Materials Science Forum, Vols. 600-603, pp. 89-94, 2009