C-V and DLTS Analyses of Trap-Induced Graded Junctions: The Case of Al+ Implanted JTE p+n 4H-SiC Diodes
Capacitance versus Voltage (C-V) and Deep Level Transient Spectroscopy (DLTS) measurements of Al+ implanted p+n diodes with Al+ implanted Junction Termination Extension are here studied. These diodes present C-V characteristics like graded junction for low forward bias values, i.e. > 0.4 V , or like abrupt junctions for large reverse bias, i.e. between 0.4V and -10V. The depth range of the graded junction, computed by the capacitance values, is much larger than the simulated tail of the ion implanted Al+ profile. DLTS spectra have been measured both in injection and standard configuration and always show minority carrier traps in the temperature range 0-300K. Three are the minority carrier related peaks, one attributed to the Al acceptor and the others to the D and D1 defects. The depth distribution of these hole traps will be discussed with respect to the apparent carrier concentration, obtained by C-V analysis.
Amador Pérez-Tomás, Philippe Godignon, Miquel Vellvehí and Pierre Brosselard
F. Fabbri et al., "C-V and DLTS Analyses of Trap-Induced Graded Junctions: The Case of Al+ Implanted JTE p+n 4H-SiC Diodes", Materials Science Forum, Vols. 615-617, pp. 469-472, 2009