High-Temperature Reliability Assessment of 4H-SiC Vertical-Channel JFET Including Forward Bias Stress


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In this work, we report the most recent reliability results of the 1200-V SiC vertical-channel JFETs (VJFETs) under reverse and forward bias of the gate-source diode at temperatures up to 200 °C. The preliminary results indicate that continuous forward bias stress of the gate-source diode at 200 °C for 112 hours produced no observable change in the forward conduction or transient or reverse blocking characteristics of the vertical-channel JFET. This preliminary result suggests that devices based on this structure, such as the enhancement-mode (normally off) SiC VJFET, may not be effected by the recombination enhanced defect creation process and the associated increase in on-resistance, related to body-diode conduction in the SiC DMOSFET and the SiC lateral-channel depletion-mode JFET. Since the vertical-channel JFET has no body diode, no degradation is possible from the reverse conduction mode of operation.



Materials Science Forum (Volumes 615-617)

Edited by:

Amador Pérez-Tomás, Philippe Godignon, Miquel Vellvehí and Pierre Brosselard






L. Cheng et al., "High-Temperature Reliability Assessment of 4H-SiC Vertical-Channel JFET Including Forward Bias Stress", Materials Science Forum, Vols. 615-617, pp. 723-726, 2009

Online since:

March 2009




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