Fabrication of SiC JFET-Based Monolithic Integrated Circuits

Abstract:

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We report fabrication of lateral, n-channel, depletion-mode, junction-field-effect-transistor (JFET) monolithic analog integrated circuits (ICs) in 6H-SiC. Ti/TaSi2/Pt forms the contact metalization, Ti/Pt the interconnect metal, and the SiO2/Si3N4/SiO2 interlayer dielectric. The threshold voltage and pinch off current indicate that the actual channel doping and thickness is close to the nominal values specified. The wafer yield for good circuits of a single-stage differential amplifier is 54% out of 46 copies.

Info:

Periodical:

Materials Science Forum (Volumes 645-648)

Edited by:

Anton J. Bauer, Peter Friedrichs, Michael Krieger, Gerhard Pensl, Roland Rupp and Thomas Seyller

Pages:

1115-1118

DOI:

10.4028/www.scientific.net/MSF.645-648.1115

Citation:

X. A. Fu et al., "Fabrication of SiC JFET-Based Monolithic Integrated Circuits", Materials Science Forum, Vols. 645-648, pp. 1115-1118, 2010

Online since:

April 2010

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Price:

$35.00

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