Morphology Improvement of Step Bunching on 4H-SiC Wafers by Polishing Technique

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In this paper, we report a new polishing technique regarding the elimination of step bunching on the silicon carbide (SiC) surface. The step bunching generation is often observed as frequent phenomenon on the surface of SiC epilayers grown on low off-angle (0001) SiC wafers and on SiC devices after annealing to activate the dopants. We polished the step bunching surface using a chemical mechanical polishing (CMP) technique reported in a previous study, and we succeeded to improve the morphology with a flat and smooth surface which showed a small Rms value of around 0.1nm. We especially found an excellent polishing effect for the control of leakage current in reverse I-V characteristics of SiC Schottky barrier diodes (SBD).

Info:

Periodical:

Materials Science Forum (Volumes 645-648)

Edited by:

Anton J. Bauer, Peter Friedrichs, Michael Krieger, Gerhard Pensl, Roland Rupp and Thomas Seyller

Pages:

763-765

DOI:

10.4028/www.scientific.net/MSF.645-648.763

Citation:

T. Kato et al., "Morphology Improvement of Step Bunching on 4H-SiC Wafers by Polishing Technique", Materials Science Forum, Vols. 645-648, pp. 763-765, 2010

Online since:

April 2010

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$35.00

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