Flat and well-ordered surfaces of silicon carbide (SiC) substrates are important for electronic devices. Furthermore, researchers have reported that 4H-SiC surface roughness increases by step-bunching during epitaxial growth and annealing. Degradation of device properties induced by surface roughening is of great concern. Therefore, a method to reduce this surface roughening is requested. We have developed a damage-free planarization method called catalyst-referred etching (CARE). In this paper, we planarized 4H-SiC substrates and evaluated the processed surface before and after the epitaxial growth. Then, we reduced the step-bunching on the epi-wafer surface and determined the electrical properties of the Schottky barrier diodes (SBD) on the processed surface.