Performance of Solder Bond on Thermal Mismatch Stresses in Electronic Packaging Assembly


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Thermo-mechanical stresses have been considered one of the major concerns in electronic Packaging assembly structural failure. The interfacial stresses are often caused by the thermal mismatch stresses induced by the coefficient of thermal expansion (CTE) difference between materials, typically during the high temperature change in the bonding process. This research work examined the effect of bond layer on thermal mismatch interfacial stresses in a bi-layered assembly. The paper verified the existing thermal mismatch solder bonded bi-layered analytical model using finite element method (FEM) simulation. The parametric studies were carried out on the effect of change of bond layer properties in order to provide useful references for interfacial stress evaluation and the electronic packaging assembly design. These parameters included CTE, temperature, thickness, and stiffness (compliant and stiff bond) of the bond layer. The recent development on lead free bonding material was being reviewed and found to have enormous potential and key role to address the future electronic packaging assembly reliability.



Materials Science Forum (Volumes 773-774)

Edited by:

A. Kiet Tieu, Hongtao Zhu and Qiang Zhu




D. Sujan et al., "Performance of Solder Bond on Thermal Mismatch Stresses in Electronic Packaging Assembly", Materials Science Forum, Vols. 773-774, pp. 242-249, 2014

Online since:

November 2013




[1] L. Li, X. -s. Ma and X. Zhou, International Conference on Electronic Packaging Technology & High Density Packaging, IEEE( 2009)August10-13, Beijing, China.

[2] P. J. Wang and C.C. Lee. Transcations on Components and Packaging Technologies, 33(1)(2010).

[3] M.F.B. Achour and A. Bar-Cohen, Electronic Components and Technology Conference, IEEE(1999).

[4] M. Y. Tsai, Transcations on Components and Packaging Technologies, 33(1)(2010).

[5] E. Suhir, Journal of Applied Mechanics, Vol. 53, p.657 – 660 (1986).

[6] E. Suhir, ASME Journal of Applied Mechanics Vol. 56, pp.595-600(1989).

[7] D. Sujan, M. V. V. Murthy, K. N. Seetharamu and A. Y. Hassan, 6th Int. Conf., Euro2005, (2005) Berlin, Germany.

[8] D. Sujan, research colloquium in Mechanical Engineering, University of Science Malaysia. p.170 (2005).

[9] Y. Wei, Office of Scientific and Technical Information. Pp. 1(1999).

[10] D. Sujan, W. E. Dereje,M. Murthy and K. N. Seetharamu. Journal of Eletronic Packaging, Vol. 133 041014-1(2011).

[11] W. F. Schmidt, Mechanical Design Considerations, in Advanced Electronic Packaging, W.D. Brown, Edited John Wiley and Sons (1999), pp.216-265.

[12] M. Vujošević, Journal of Theoretical and Applied Mechanics, 35(1-3): pp.305-322(2008).

[13] Y. Wei, Office of Scientific and Technical Information. p.1(1999).

[14] S. Bezuk, Flip Chip Challenges, in HDI Magazine, Kyocera America. pp.1-6(2000).

[15] T. Yamamoto and K. I. Tsubone, Fujitsu Science and Technical Journal, 43(1): pp.50-58(2007).

[16] C. L. Chuang, Journal of Electronic Materials, 37(11): p.1742(2008).

[17] P. J. Wang, J.S. Kim and C.C. Lee, Journal of Electronic Materials, 38(10): pp.2106-2111(2009).

[18] R. I. Made, Journal of Electronic Materials, 38(2): pp.365-371(2009).

[19] S. S. Too, 25th IEEE SEMI-THERM Symposium, IEEE. p.186(2009).

[20] P. J. Wang and C.C. Lee, IEEE Transactions on Components and Packaging Technologies, 33(1): pp.10-14(2010).

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