Threshold Voltage Instabilities of Present SiC-Power MOSFETs under Positive Bias Temperature Stress


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We study the threshold voltage (Vth) instability of commercially available silicon carbide (SiC) power MOSFETs or prototypes from four different manufacturers under positive bias temperature stress (PBTS). A positive bias near the Vth causes a threshold voltage shift of 0.7 mV per decade in time per nanometer oxide thickness in the temperature range between-50 °C and 150 °C. Recovery at +5 V after a 100 s +25 V gate-pulse causes a recovery between-1.5 mV/dec/nm and-1.0 mV/dec/nm at room temperature and is decreasing with temperature. All devices show similar stress, recovery and temperature dependent behavior indicating that the observed Vth instabilities are likely a fundamental physical property of the SiC-SiO2 system caused by electron trapping in near interface traps. It is important to note that the trapping is not causing permanent damage to the interface like H-bond-breakage in silicon based devices and is nearly fully reversible via a negative gate bias.



Edited by:

Fabrizio Roccaforte, Francesco La Via, Roberta Nipoti, Danilo Crippa, Filippo Giannazzo and Mario Saggio






G. Rescher et al., "Threshold Voltage Instabilities of Present SiC-Power MOSFETs under Positive Bias Temperature Stress", Materials Science Forum, Vol. 858, pp. 481-484, 2016

Online since:

May 2016




* - Corresponding Author

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