Determination of Performance-Relevant Trapped Charge in 4H Silicon Carbide MOSFETs

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Current-voltage characterization and thermal dielectric relaxation current (TDRC) measurements are carried out on 4H silicon carbide (SiC) n-channel MOSFETs processed with different post oxidation anneals (POAs) in O2, N2O, and NO atmospheres at high temperature. In all samples we observe a distinct peak at a temperature of 70 K in the TDRC spectra due to a defect close to the conduction band of 4H-SiC having a high density of states (>1013 cm-2eV-1). We show that this defect is related to the degradation of the device performance such as the MOSFET conductivity. Comparing the different POAs, NO strongly reduces the density of states close to the conduction band and thus increases the amount of free channel electrons. Based on TDRC measurements we want to suggest a method for more accurate estimation of the true channel mobility accounting for the reduced channel electron density due to trapping.

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Edited by:

Robert Stahlbush, Philip Neudeck, Anup Bhalla, Robert P. Devaty, Michael Dudley and Aivars Lelis

Pages:

277-280

Citation:

F. Rasinger et al., "Determination of Performance-Relevant Trapped Charge in 4H Silicon Carbide MOSFETs", Materials Science Forum, Vol. 924, pp. 277-280, 2018

Online since:

June 2018

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$38.00

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