Oxygen Pressure Controlled Oxidation for Gate Insulator Process of SiC MOSFETs


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For the improvement of a SiC/SiO2 interface of SiC-MOSFET, we examined O2 partial pressure (PO2) controlled (OPC) oxidation process for the gate oxide formation. The OPC oxidation process has a potential to reduce interface state density (Dit) at SiC/SiO2 interface by using appropriate PO2 and oxidation temperature. However the process requires rapid thermal annealing which is not suitable for mass production. Thus we investigated the process using furnace. First, we optimized the OPC oxidation process for the furnace to realize low interface defect density. Secondly, we confirmed that reduction of Dit was determined by desorption of excess carbon in OPC process by the C–ψs measurement and X-ray photoelectron spectroscopy. Finally, a DMOSFET was fabricated using optimized OPC process. We measured the transfer characteristics, and found that the drain current with OPC was larger than without OPC process.



Edited by:

Robert Stahlbush, Philip Neudeck, Anup Bhalla, Robert P. Devaty, Michael Dudley and Aivars Lelis




K. Kobayashi et al., "Oxygen Pressure Controlled Oxidation for Gate Insulator Process of SiC MOSFETs", Materials Science Forum, Vol. 924, pp. 453-456, 2018

Online since:

June 2018




* - Corresponding Author

[1] Afanasev, V.V., Bassler, M., Pensl, G., & Schulz, M., Intrinsic SiC/SiO2 Interface States. physica status solidi (a), 162 (1997), 321-337.

DOI: https://doi.org/10.1002/1521-396x(199707)162:1<321::aid-pssa321>3.0.co;2-f

[2] Rudenko, T.E., Osiyuk, I.N., Tyagulski, I.P., Ólafsson, H.Ö., & Sveinbjörnsson, E.Ö., Interface trap properties of thermally oxidized n-type 4H–SiC and 6H–SiC. Solid-state electronics, 49 (2005) 545-553.

DOI: https://doi.org/10.1016/j.sse.2004.12.006

[3] Mori, Y., Hisamoto, D., Tega, N., Matsumura, M., Yoshimoto, H., Shima, A., & Shimamoto, Y., Effects of interface properties in SiC MOSFETs on reliability. In Physical and Failure Analysis of Integrated Circuits (IPFA), 2015 IEEE 22nd International Symposium on the (pp.68-71.

DOI: https://doi.org/10.1109/ipfa.2015.7224335

[4] Chung, G.Y., Tin, C.C., Williams, J.R., McDonald, K., Chanana, R.K., Weller, R.A., ... & Palmour, J.W., Improved inversion channel mobility for 4H-SiC MOSFETs following high temperature anneals in nitric oxide. IEEE Electron Device Letters, 22 (2001).

DOI: https://doi.org/10.1109/55.915604

[5] Chung, G.Y., Tin, C.C., Williams, J.R., McDonald, K., Di Ventra, M., Pantelides, S.T., ... & Weller, R.A., Effect of nitric oxide annealing on the interface trap densities near the band edges in the 4H polytype of silicon carbide. Applied Physics Letters, 76 (2000).

DOI: https://doi.org/10.1063/1.126167

[6] Kikuchi, R. H., & Kita, K., Fabrication of SiO2/4H-SiC (0001) interface with nearly ideal capacitance-voltage characteristics by thermal oxidation. Applied Physics Letters, 105 (2014) 032106.

DOI: https://doi.org/10.1063/1.4891166

[7] Kikuchi, R. H., & Kita, K., Interface-reaction-limited growth of thermal oxides on 4H-SiC (0001) in nanometer-thick region. Applied Physics Letters, 104 (2014) 052106.

DOI: https://doi.org/10.1063/1.4864284

[8] Yoshioka, H., Nakamura, T., & Kimoto, T., Generation of very fast states by nitridation of the SiO2/SiC interface. Journal of Applied Physics, 112 (2012) 024520.

DOI: https://doi.org/10.1063/1.4740068

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