High-Mobility SiC MOSFETs Using a Thin-SiO2/Al2O3 Gate Stack
We report the development of a low-temperature (600 °C) gate oxidation approach to minimize the density of interface traps (DIT) at the SiC/SiO2 interface, ultimately leading to a significantly higher channel mobility in SiC MOSFETs of 81 cm2·V-1·s-1, >11x higher than devices fabricated alongside but with a conventional 1150 °C gate oxide. We further report on the comparison made between the DIT and channel mobilities of MOS capacitors and n-MOSFETs fabricated using the low-and high-temperature gate oxidation.
Robert Stahlbush, Philip Neudeck, Anup Bhalla, Robert P. Devaty, Michael Dudley and Aivars Lelis
J. Urresti et al., "High-Mobility SiC MOSFETs Using a Thin-SiO2/Al2O3 Gate Stack", Materials Science Forum, Vol. 924, pp. 494-497, 2018