Surface Engineering of SiC through Nanogrinding and CMP

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Processing silicon carbide (SiC) wafers to achieve an epi-ready quality finish typically requires many lapping and a very long chemical mechanical polishing (CMP) steps. In this paper, we report the thinning down of 6” SiC wafers to sub-nanometer surface finish in less than two hours. Three process steps (rough grinding, nanogrinding and CMP) are involved. Rough grinding thins down the wafer with fast feed rate and maintain excellent flatness. Nanogrinding allows the surface finish to improve down to a few nanometers. The last CMP step provides high planarization efficiency. Overall the throughput of SiC processing is substantially increased over current market solutions.

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Edited by:

Robert Stahlbush, Philip Neudeck, Anup Bhalla, Robert P. Devaty, Michael Dudley and Aivars Lelis

Pages:

539-542

Citation:

R. Vacassy et al., "Surface Engineering of SiC through Nanogrinding and CMP", Materials Science Forum, Vol. 924, pp. 539-542, 2018

Online since:

June 2018

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$38.00

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DOI: https://doi.org/10.1016/s0921-5107(98)00528-5

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