Comprehensive Evaluation of Bias Temperature Instabilities on 4H-SiC MOSFETs Using Device Preconditioning

Abstract:

Article Preview

In comparison to silicon based devices, MOSFETs based on silicon carbide show more complex threshold voltage variations caused by positive and negative gate bias stress. We show that the majority of the voltage shift in standard JEDEC-like bias temperature instability measurements originates from stress independent measurement parameters like timing and switching conditions. A more sophisticated bias temperature instability measurement technique using device preconditioning is presented allowing for more accurate and nearly delay time independent extraction of the permanent voltage shift component within typical industrial timescales.

Info:

Periodical:

Edited by:

Robert Stahlbush, Philip Neudeck, Anup Bhalla, Robert P. Devaty, Michael Dudley and Aivars Lelis

Pages:

671-675

Citation:

G. Rescher et al., "Comprehensive Evaluation of Bias Temperature Instabilities on 4H-SiC MOSFETs Using Device Preconditioning", Materials Science Forum, Vol. 924, pp. 671-675, 2018

Online since:

June 2018

Export:

Price:

$38.00

* - Corresponding Author

[1] E. Zhang et al. ,IEEE Transactions on Device and Materials Reliability 12, 391–398, (2012).

[2] A. J. Lelis, et al, IEEE Transactions on Electron Devices, vol. 55, no. 8, p.1835–1840, (2008).

[3] A. Stoneham, Reports on Progress in Physics, vol. 44, no. 12, p.1251, (1981).

[4] C. Kittel, Introduction to solid state physics. Wiley, (2005).

[5] T. Grasser, Bias Temperature Instability for Devices and Circuits, 447-481, Springer (2014).

[6] Procedure for Wafer-Level DC Characterization of BTI, JEDEC Standard (2015).

[7] G. Rescher, International Electron Devices Meeting, IEEE (2016).