Reliability and Ruggedness of 1200V SiC Planar Gate MOSFETs Fabricated in a High Volume CMOS Foundry


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This paper presents the performance, reliability and ruggedness characterization of 1200V, 80mΩ rated SiC planar gate MOSFETs, fabricated in a high volume, 150mm silicon CMOS foundry. The devices showed a specific on-resistance of 5.1 mΩ.cm2 at room temperature, increasing to 7.5 mΩ.cm2 at 175 °C. Total switching losses were less than 300μJ (VDD = 800V, ID = 20A). The devices showed excellent gate oxide reliability with VTH shifts under 0.2V for extended HTGB stress testing at 175 °C for up to 5500 hours (VGS = 25V) and 2500 hours (VGS = -10V). Ruggedness performance such as unclamped inductive load switching and short circuit capability are also discussed.



Edited by:

Robert Stahlbush, Philip Neudeck, Anup Bhalla, Robert P. Devaty, Michael Dudley and Aivars Lelis




S. Chowdhury et al., "Reliability and Ruggedness of 1200V SiC Planar Gate MOSFETs Fabricated in a High Volume CMOS Foundry", Materials Science Forum, Vol. 924, pp. 697-702, 2018

Online since:

June 2018




* - Corresponding Author

[1] N. Iwamuro and T. Laska, IGBT History, State-of-the-Art, and Future Prospects, IEEE Trans. Electron Devices, 64 (2017) 741–752.


[2] S. Banerjee, K. Matocha, K. Chatty, J. Nowak, B. Powell, D. Gutierrez, and C. Hundley, Manufacturable and rugged 1.2 kV SiC MOSFETs fabricated in high-volume 150mm CMOS fab, Proc. Int. Symp. Power Semicond. Devices and ICs, (2016) 279-282.


[3] D. S. Kuo, C. Hu, and M. H. Chi, dV/dt Breakdown in power MOSFET's, IEEE Electron Device Lett., 4 (1983) 1–2.


[4] A. J. Lelis, R. Green, D. B. Habersat, and M. El, Basic Mechanisms of Threshold-Voltage Instability and Implications for Reliability Testing of SiC MOSFETs, IEEE Trans. Electron Devices, 62 (2015) 316–323.


[5] Z. Chbili, K. P. Cheung, J. P. Campbell, J. Chbili, M. Lahbabi, D. E. Ioannou, and K. Matocha, Time Dependent Dielectric Breakdown in High Quality SiC MOS Capacitors, Mater. Sci. Forum, 858 (2016) 615–618.


[6] J. McPherson, V. Reddy, K. Banerjee, and Huy Le, Comparison of E and 1/E TDDB models for SiO2 under long-term/low-field test conditions,, in Proc. IEDM, (1998) 171–174.


[7] P. A. Losee, A. Bolotnikov, L. C. Yu, G. Dunne, D. Esler, J. Erlbaum, B. Rowden, A. Gowda, A. Halverson, R. Ghandi, P. Sandvik, L. Stevanovic, and R. Hristov, SiC MOSFET design considerations for reliable high voltage operation, Proc. IRPS, (2017).