Influences of Bias Interruption and Reapplication on High-Temperature Threshold-Voltage Shifts of SiC DMOSFETs
For the paper, we studied how bias stress interruption and reapplication influences threshold voltage (VT) drift results in SiC DMOSFETs during 175°C bias-temperature instability (BTI) tests. Bias interruptions of even short durations were found to result in significant loss of observed VT drift, although reapplying the stress bias for a short time immediately before making the post-stress measurement resulted in a significant recovery of the lost drift. The fractional VT drift (i.e., the ratio of “observed” to “actual” drift) was found to behave similarly to the case of 25°C bias stressing, with an apparent empirical relationship relating to the square of the reapply time, divided by interrupt time. Although questions of bias-stressing at high temperature with room-temperature measurement remain unresolved for now, these results continue to support the feasibility of stress bias reapplication to counteract the loss in VT drift due to delays or interruptions between stressing and measurement (which are a practical limitation imposed by the necessities of batch testing for qualification in a production environment).
Robert Stahlbush, Philip Neudeck, Anup Bhalla, Robert P. Devaty, Michael Dudley and Aivars Lelis
D. B. Habersat et al., "Influences of Bias Interruption and Reapplication on High-Temperature Threshold-Voltage Shifts of SiC DMOSFETs", Materials Science Forum, Vol. 924, pp. 743-747, 2018