Materials Science Forum

Preface

Thu, 21 May 2026 00:00:00 +0200

Publication date: 21 May 2026
Source: Materials Science Forum Vol. 1193

Comparative Study on Grinding Behavior of C-Face and Si-Face in Laser-Sliced 4H-SiC Wafers

Thu, 21 May 2026 00:00:00 +0200

Publication date: 21 May 2026
Source: Materials Science Forum Vol. 1193
Author(s): Bi Xue Li, Xing Zhang, Qiu Chen, Lin Lin Che, Jian Fei Zhang, Hao Yu Fan, Xian Gang Xu, Rong Kun Wang, Xiu Fang Chen
With the growing application of wide-bandgap semiconductors such as SiC in power electronics, efficient and low-damage machining of large-diameter, high-quality 4H-SiC wafers has become a critical research priority. This study systematically compares the grinding behavior of the C-and Si-faces of laser-sliced 4H-SiC wafers and reveals the effect of crystallographic anisotropy on tool wear. In the experiments, a picosecond laser was used to induce internal crystal modification, and multiple pairs of 12-inch high-purity semi-insulating crystals and wafers were obtained through ultrasonic separation. These wafers were subsequently ground using #800/#8000 resin-bonded diamond wheels. Material removal and wheel wear were recorded in real time, and the wheel wear ratio (W/M) was adopted as the key evaluation metric. Nanoindentation and white-light interferometry were further employed to characterize the mechanical properties and surface morphology of the two crystal faces. Results show that in both rough and fine grinding, the C-face demonstrates superior material removal performance despite its higher hardness, whereas the Si-face is more prone to wheel degradation. For thin wafers, residual laser focus near the surface further aggravates wheel wear. These findings establish a link between crystallographic anisotropy, laser-modified layer position, and wheel wear behavior, providing an experimental foundation for clarifying the underlying mechanisms and developing face-specific grinding strategies for high-quality SiC wafer fabrication.

Effects of Processing Passes on Laser-Sliced SiC

Thu, 21 May 2026 00:00:00 +0200

Publication date: 21 May 2026
Source: Materials Science Forum Vol. 1193
Author(s): Jian Fei Zhang, Bi Xue Li, Qiu Chen, Lin Lin Che, Xing Zhang, Hao Yu Fan, Yang Yang Jia, Jia Wei Wang, Yu Feng Xue, Rong Kun Wang, Xiu Fang Chen
Silicon carbide (SiC), a representative of next-generation wide-bandgap semiconductors, exhibits enormous application potential in fields such as new energy vehicles, aerospace, and photovoltaic power generation. Conventional cutting methods based on diamond wire sawing suffer from high material loss and are prone to causing fractures. In contrast, laser slicing, as a kerf-free processing technology, enables the acquisition of high-quality wafers with minimal material removal. This study systematically investigates the effect of processing cycles on crack propagation and delamination strength during laser slicing of SiC. The experimental results demonstrate that under optimized parameters, an appropriate number of processing cycles can achieve successful wafer separation while maintaining surface integrity, reducing material loss, and lowering delamination strength. The established processing window provides practical guidance for improving SiC slicing quality and holds significant implications for advancing innovative wafer manufacturing technologies in power electronics applications.

Feasibility Study of SiC Wafer Reutilization Process through Laser Splitting and Bonding Techniques

Thu, 21 May 2026 00:00:00 +0200

Publication date: 21 May 2026
Source: Materials Science Forum Vol. 1193
Author(s): Takanori Tanaka, Kyohei Akiyoshi, Kazumasa Iwanaga, Shunta Takahashi, Hiroshi Watanabe, Kenichi Hamano, Akihiko Furukawa
We propose a novel SiC wafer recycling process that employs the laser splitting and wafer bonding techniques. The process allows us to attain the recycled SiC wafers suitable for conventional device processes, leading to the reduction of SiC device costs and environmental burdens. Preliminary evaluations were conducted on the key technologies of the process: surface activated bonding and laser splitting for SiC wafers. The bonding interface was confirmed to withstand the stresses encountered during device manufacturing thanks to the recrystallization of the interface layer. The electrical characteristics of MOSFETs thinned using laser splitting showed no significant difference compared to those thinned by conventional grinding. These results demonstrate that the proposed process is a feasible technique that offers a cost-effective and eco-friendly solution for SiC power device production.

Impacts of Wafer Thinning Process Using Laser Slice Technique on Silicon Carbide Device Characteristics

Thu, 21 May 2026 00:00:00 +0200

Publication date: 21 May 2026
Source: Materials Science Forum Vol. 1193
Author(s): Kyohei Akiyoshi, Takanori Tanaka, Shunta Takahashi, Kazumasa Iwanaga, Kenichi Hamano, Akihiko Furukawa
A laser slicing technique is an attractive alternative to grinding for thinning SiC wafers. This method has the potential to enable the reutilization of SiC wafers and reduce the waste generated during the grinding process. This paper comprehensively investigates the technical feasibility of laser slicing for the fabrication of SiC power devices. SiC JBS samples fabricated with laser irradiation revealed that by selecting the appropriate laser conditions, we can employ the technique without adversely affecting the JBS leakage current characteristics. Additionally, we fabricated SiC MOSFETs through wafer thinning using the laser slicing technique. The key electrical characteristics of the MOSFETs, including IGSS, IDSS, Vth and VDS(on), showed no differences compared to those fabricated using conventional grinding. These results indicate that laser slicing is a highly promising thinning technique for the fabrication of SiC power devices.

A Study on the Synthesis and Evaluation of Si/SiC Powders for SiC Wafers Fabrication and Si-Based Devices

Thu, 21 May 2026 00:00:00 +0200

Publication date: 21 May 2026
Source: Materials Science Forum Vol. 1193
Author(s): Myung Beom Park, Jungwon Kim, Yigil Cho, Yun Ho Kim, Sam Jong Choi
This study delves into the synthesis of high-purity SiC powders utilizing two distinct silicon (Si) sources of recycled Si wafers and back-grind wastewater—both of which are abundant by-products in semiconductor manufacturing processes. The synthesis involved the high-temperature reaction of these Si sources with ultra-high-purity graphite (>6N) at temperatures exceeding 2100°C. The resulting α-phase SiC powders derived from previously used Si wafers demonstrated unparalleled quality, achieving a purity level surpassing 99.9999% and exhibiting particle sizes exceeding 500 µm. These characteristics render them highly suitable for the fabrication of SiC wafers, a cornerstone of advanced semiconductor applications. This research underscores the potential of leveraging industrial by-products as sustainable Si sources for SiC synthesis, highlighting the superiority of α-phase SiC produced from recycled Si wafers in high-purity applications.

Damage-Free Dicing of SiC Substrate Using High-Pressure SF6 Plasma: The Time Dependence of Processed Groove Profiles

Thu, 21 May 2026 00:00:00 +0200

Publication date: 21 May 2026
Source: Materials Science Forum Vol. 1193
Author(s): Yuken Matsumura, Shunto Iden, Daisetsu Toh, Jumpei Yamada, Yasuhisa Sano
Plasma chemical vaporization machining (PCVM) is a high-rate etching method that uses atmospheric-pressure plasma. Its application to the plasma dicing of SiC wafers is anticipated. However, since the reaction is mainly driven by neutral radicals, it is difficult to maintain anisotropy, and issues such as side etching are of concern. In this study, PCVM processing was performed using SF₆ gas with a Ni mask to investigate vertical and lateral etching behaviors. We achieved vertical etching of 100 µm within approximately 35 minutes, and lateral side etching of about 50 µm. The lateral etch rate remained nearly constant, whereas the vertical etch rate was initially high but decreased as the etching progressed, approaching the lateral rate. Finite element-based electrostatic field analysis revealed that, as the etching depth increased, electric field shielding by the mask weakened the field at the bottom of the trench, leading to a transition toward neutral radical-dominated reactions.

Correlation Study of Physical and Optical Total Thickness Variation in 4H-SiC Substrates

Thu, 21 May 2026 00:00:00 +0200

Publication date: 21 May 2026
Source: Materials Science Forum Vol. 1193
Author(s): David M. Lynch, Gregory L. Keaton, Christopher A. Lee, Alexander T. Bean
Accurate total thickness variation (TTV) measurement is essential for silicon carbide (SiC) wafer manufacturing and process control. This work evaluates the accuracy of interferometric TTV measurements using the Corning Tropel FlatMaster MSP system, benchmarked against a dual-source chromatic white light (CWL) profilometer. We investigate the influence of spatial refractive index variation on interferometric accuracy by comparing MSP and CWL results. The analysis reveals high MSP repeatability with small deviations linked to index variation. These trends provide a framework for interpreting interferometric TTV data and improving metrology practices for SiC substrates.

Impact of Ambient Conditions on Oxide Thickness Distribution on 4H-SiC in Thermal Oxidation Furnace

Thu, 21 May 2026 00:00:00 +0200

Publication date: 21 May 2026
Source: Materials Science Forum Vol. 1193
Author(s): Tamara Fidler, Patrick Schmid
4H-SiC wafers were processed in thermal oxidation furnace and impact of oxidation temperature up to 1500 °C, processing pressure and different gaseous ambient on oxide thickness distribution was investigated. Beside the impact of thermal distribution within oxidation furnace, an additional effect on oxide thickness distribution has been observed, due to promotion of oxidation rate in the center of the wafer. Within this work, we have examined which influence processing parameters have on described effect, specific for SiC oxidation.

Strain Relief of Silicon Carbide Substrates(4H-SiC) by Wet Etching

Thu, 21 May 2026 00:00:00 +0200

Publication date: 21 May 2026
Source: Materials Science Forum Vol. 1193
Author(s): Norbert Bay, Athul Rathnakar, Xavier Gay, Wyatt Engler, Rahim Hamid, Franck Delahaye, Oliver Whear, Vishal A. Shah, Holger Kuehnlein
Strain relief etching is a critical wet process technique use in high volume manufacturing of semiconductor substrates and device wafers. The goal of a strain relief etch is application dependent but can generally be considered for removal of warp/bow or improving mechanical strength by removing sub-surface damage thereby optimizing yields. Silicon Carbide (SiC) has a high chemical resistance which has blocked SiC wafer manufacturers from using strain relief etching to date. In this work, we demonstrate strain relief etching using an Advanced Chemical Etching (ACE) process of the full wafer surface on commercial grade 4H-SiC wafers and poly-SiC wafers at high etch rates (μm’s/hr) which enable ACE as a production technique. The data shows a 4 times improvement of breakage strength, from 13 to 55N, in laser split wafers. Bow and warp of ground wafers is reduced from 70/250µm to -5/25µm approx. respectively, matching Chemical Mechanical Polished (CMP) wafers which is the industrial method for preparing wafers. Thus showing the potential of stronger, flatter wafers being available for chemical mechanical polishing.

CMOS-Compatible Pore Nucleation on 4H-SiC Si-Face via Reactive Ion Etching for Homogeneous Electrochemical Etching

Thu, 21 May 2026 00:00:00 +0200

Publication date: 21 May 2026
Source: Materials Science Forum Vol. 1193
Author(s): Georg Pfusterschmied, Michael Kusolitsch, Christopher Zellner, Marco Perazzi, Ting Qiang Yang, Ulrich Schmid
Electrochemical etching (ECE) of silicon carbide is a powerful route to porous 4H‑SiC. Yet, reliable pore initiation on the Si-face typically requires additional sophisticated pre-conditioning (e.g. masked KOH etching, metal-assisted photochemical etching (MAPCE), focused ion beam (FIB) milling), limiting industrial adoption. We demonstrate a simple, CMOS‑compatible pre‑conditioning based on short reactive‑ion‑etching (RIE) steps (10–30 s, SF₆/O₂) that reproducibly nucleate pores on the Si‑face of highly doped 4H‑SiC (resistivity < 0.02 Ω·cm) and enable homogeneous ECE in HF/ethanol without UV illumination. Surface roughness increases modestly with RIE time (Ra ≈ 1.3 nm to 4.0 nm), while subsequent ECE does not significantly degrade topography. SEM cross‑sections reveal continuous porous layers; image‑based quantification shows enhanced vertical pore alignment with longer RIE duration. A stepwise voltage program (11.5 V → 8.5 V → 11.5 V) yields stable current transients during etching. Eliminating noble metals and lithography reduces contamination risk. It improves process compatibility with front‑end manufacturing while remaining synergistic with our previously established ECE process flows and high‑temperature reorganisation of thin, porous SiC layers.

BPD-Free Dicing of Epitaxial SiC Wafers Using Water Jet Guided Laser

Thu, 21 May 2026 00:00:00 +0200

Publication date: 21 May 2026
Source: Materials Science Forum Vol. 1193
Author(s): Shunya Hirano, Hyuk Kim, Satoru Takahashi, Shuzo Masui, Noboru Ohtani, Kozo Abe
Silicon carbide (SiC) wafers are essential for next-generation power devices, however conventional dicing methods often induce cracks and Basal Plane Dislocations (BPDs), reducing device reliability. This study demonstrates BPD-free dicing of epitaxial SiC wafers using Water jet Guided Laser (WGL) processing. Full-thickness cutting was performed on 350 μm-thickness wafers with a 10 μm-thickness epitaxial layer using a YAG laser (532 nm wavelength, 200 ns pulse width, 10 kHz repetition rate, 30–80 W output) on an LB300 system. BPD evaluation was carried out by X-ray topography (XRT) with the-1-128 reflection before and after cutting. The results showed no generation or propagation of new BPDs, and pre-existing BPDs did not glide, confirming that WGL processing enables BPD-free machining. These results are attributed to the ablation-based nature of WGL with water assistance, which avoids mechanical stress on epitaxial SiC wafers.

Study on Electrochemical Assisted Fixed-Abrasive Lapping for Wafer Thinning of Monocrystalline Silicon Carbide Wafer

Thu, 21 May 2026 00:00:00 +0200

Publication date: 21 May 2026
Source: Materials Science Forum Vol. 1193
Author(s): Chen Hang Wu, Chao Jun Zhang, Shao Yuan Huang, Chao Chang Arthur Chen
This study aims to develop an electrochemical assisted fixed-abrasive lapping (ECAL) process for thinning 4H-SiC wafers (C-face). Process with 20 wt% NaNO₃ electrolyte to generate a softened passivation layer has been formed and simultaneously removed by a fixed diamond lap wheel. Electrochemical tests using a potentiostat have verified 20 V as the selected experimental potential, and a significant reduction in hardness has been confirmed by nanoindentation. Under these conditions, the 4-inch wafer has achieved a material removal rate (MRR) of 3.181 μm/h with wafer quality (Bow –7.80 μm, Warp 48.50 μm, TTV 7.70 μm). When the same conditions have been applied to 6-inch wafers, an MRR of 2.457 μm/h and wafer quality (Bow –5.00 μm, Warp 36.70 μm, TTV 6.60 μm) have been obtained. These results have demonstrated the scalability of ECAL for larger SiC substrates, offering potential for next-generation device manufacturing.