Texture Control in Manufacturing of ULSI Devices


Article Preview

The rapid adoption of damascene copper processing has brought about an increased need to understand and control microstructure in the barrier, seed and electroplated copper layers during manufacture. We will discuss an in-line, x-ray diffraction based metrology for rapidly characterizing thin film polycrystalline microstructures on 300 mm silicon wafers in terms of crystallographic texture, phase composition, and film thickness. The microstructure control plays an increasingly important role in improving the performance and reliability of ULSI devices that use the damascene copper technology at 0.13-µm node and below. The problems related to delamination, stress voiding, and electromigration failures could be mitigated by the selection of proper materials, processing methods, and manufacturing tools. The optimum process would result in a tailored microstructure of barrier/seed/electroplated copper aggregate. At the same time, the microstructure could be used as an internal sensor, sensitive to process excursions and providing guidance for the corrective actions. The texture and crystallographic phase data can be used as a direct measure of the deposition process in terms of film quality, reproducibility, and stability over time. The spatial distribution of crystallographic texture and phase can be measured on a single wafer in order to check wafer uniformity. More importantly, the same measurements can be carried out at predetermined intervals on wafers from a single deposition tool, and the results used to create a database that can be applied to trend charting and tool qualification. Examples of microstructure control in damascene copper processing include: process development and qualification, process control and stability, deposition tool qualification, and on-line R&D. Examples of texture control will refer to materials and processes typical of damascene copper technology for ULSI. A typical processing route includes the PVD deposition of a barrier layer and copper seed layer, followed by copper electroplate (EP), anneal, and chemical-mechanical planarization (CMP). All the processing steps affect the texture of annealed copper, and therefore affect directly the performance of interconnects.



Solid State Phenomena (Volume 105)

Edited by:

C. Esling, M. Humbert, R.A. Schwarzer and F. Wagner






K. J. Kozaczek "Texture Control in Manufacturing of ULSI Devices", Solid State Phenomena, Vol. 105, pp. 101-106, 2005

Online since:

July 2005





[1] H. S. Goindi, C.S. Shin, M. Frederick, Y. Shusterman, H. Kim, I. Petrov, and G. Ramanath: Mat. Res. Soc. Symp. Proc. Vol. 648 (2001), p. P11. 37. 1.

[2] K. Abe, Y. Harada, H. Onoda: IEEE 36th Ann. Int. Reliability Phys. Symp., Reno, Nevada (1998), p.342.

[3] C. Ryu, K-W. Kwon, A.L.S. Loke, H. Lee, T. Nogami, V. Dubin, R. A. Kavari, G.W. Ray, and S. S. Wong: IEEE Trans. Electron Devices Vol 46 No6 (1999), p.1113.

DOI: 10.1109/16.766872

[4] B.C. Valek, N. Meier, N. Tamura, R. Spolanek, R.S. Celestre, A.A. MacDowell, H.A. Padmore, J.C. Bravman, and J.R. Patel: www-als. lbl. gov.

[5] A. Sakiguchi, J. Koike, and K. Maruyama: Appl. Phys. Let. Vol. 83(10) (2002), p. (1962).

[6] J. Koike et al.: AIP Conf. Proc., Vol. 612(1) (April 15, 2002), p.169.

[7] S. Takayama, M. Oikawa, T. Himuro: Mat. Res. Symp. Proc. Vol. 795 (2004), p. U5. 11. 1.

[8] S.R. Soss, B. Gittleman, K.E. Mello, T. -M. Lu, and S.L. Lee: Mat. Res. Soc. Symo. Proc. Vol. 403 (1996), p.633.

[9] K. P. Rodbell, IBM T.J. Watson Research Center, Yorktown Heights, NY, unpublished research.

[10] L. G. Gosset, V. Arnal, S. Chhun, N, Casanova, M. Melier, J. -Ph. Reynard, X. Federspiel, J. -F. Guillamond, L. Arnaud, J. Torres: AMC 2003 (in print).

[11] L. G. Gosset, S. Chhun, A. Farcy, N. Casanove, V. Arnal, W.F. A. Besling, J. Torres: IITC 2004 (in press).

[12] E. Zschech, M. A. Meyer, E. Langer: Mat. Res. Soc. Symp. Proc. Vol. 812 (2004), p. F7. 5. 1.

[13] H. Lee, S.D. Lopatin, T. Nogami, and S. S. Wong: 1998 MRS Fall Meeting, Paper A1. 9, Boston, MA, Dec. 1, (1998).

[14] K. J. Kozaczek, C. Murray, K.P. Rodbell: these proceedings.

[15] K. Barmak, A. Gungor, A.D. Rollet, C. Cabral Jr., J.M.E. Harper: Materials Science in Semiconductor Processing Vol. 6 (2003), p.175.

[16] R. Rosenberg, D.C. Edelstein, C. -K. Hu, K.P. Rodbell: Ann. Rev. Mater. Sci. Vol. 30 (2000), p.229.

[17] D.P. Field: Proc. 12 th Int. Conf. Textures of Mat. Vol. 2 (1999), p.1309.

[18] R. Junginger, G. Elsner: J. Electroch. Soc. Vol. 135 (1988), p.2304.

[19] Q. -T. Jiang, A. frank, R.H. Havemann, V. Parihar, and M. Nowell: Symp. VLSI Tech. (2001), p.139.

[20] M.E. Gross et al.: AMC (2000), p.85.

[21] K. J. Kozaczek, R.I. Martin, L.Y. Huang, D.S. Kurtz, P.R. Moran: Characterization and. Metrology for ULSI technology (2003), p.485.

[22] E.M. Zielinski, R.P. Vinci, and J.C. Bravman: J. Appl. Phys. Vol. 76(8) (1994), p.4516.

[23] R.K. Maynard, S.J. Pearton, and R.K. Singh: J. Electroch. Soc. Vol. 149(12) (20020, p. G648.

In order to see related information, you need to Login.