Phase Locked Loop Integrated System

Abstract:

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CMOS-MEMS integration is an indispensable technique for self-calibration of electromechanical performance to make MEMS devices independent on environmental drift or fabrication errors. The goal of single-chip integration (the “holy grail” for the semiconductor timing industry) would be to include the resonator, the oscillator, the PLL and a temperature compensation circuit (TCC) on a single silicon substrate. The current structure of silicon MEMS-based devices utilizes a stacked-die arrangement, housed in a multi-chip package [1]. MEMS-based timing circuits often use PLLs, which can succumb to phase jitter and noise at higher timing frequencies. The architecture of a charge pump phase locked loop (CPPLL) is proposed in this work. It is discussed how its functional blocks influence the overall system performance. We have performed voltage-controlled oscillator (VCO) phase noise analysis and have determined the relationship between CPPLL and VCO phase noises and have discussed the requirements and results of the accomplished design.

Info:

Periodical:

Solid State Phenomena (Volume 164)

Edited by:

Andrejus H. Marcinkevičius and Algirdas V.Valiulis

Pages:

221-226

DOI:

10.4028/www.scientific.net/SSP.164.221

Citation:

J. Charlamov and R. Navickas, "Phase Locked Loop Integrated System", Solid State Phenomena, Vol. 164, pp. 221-226, 2010

Online since:

June 2010

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Price:

$35.00

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