Electronic Properties of ZnO/Si Heterojunction Prepared by ALD.
ZnO/n-Si and ZnO/p-Si heterostructures were prepared by Atomic layer deposition (ALD) and the electronic properties have been investigated by Current-Voltage (I-V), Capacitance-Voltage (C-V) and Deep level transient spectroscopy (DLTS) measurements. DLTS measurements show two dominants electron traps at the interface of the ZnO/n-Si junction with energy position at 0.07 eV and 0.15 eV below the conduction band edge, labelled E(0.07) and E(0.15), respectively, and no electrically active defects at the interface of the ZnO/p-Si junction. E(0.07) is reduced by annealing up to 400°C while E(0.15) is created at 500°C. The best heterostructure is found after heat treatment at 400°C with a substantial improvement of the current rectification for ZnO/n-Si and the formation of Ohmic contact on ZnO/p-Si. A reduction of the interface defects correlates with an improvement of the crystal structure of the ZnO film with a preferred orientation along the c-axis.
W. Jantsch and F. Schäffler
V. Quemener et al., "Electronic Properties of ZnO/Si Heterojunction Prepared by ALD.", Solid State Phenomena, Vols. 178-179, pp. 130-135, 2011