Low Power Test Pattern Design for VLSI Circuits Using Incorporate Pseudorandom and Deterministic Approach

Abstract:

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The circuits should be tested extensively during the production process, the power consumption in a circuit during test mode can be higher than that the consumption during normal operation mode. The circuits are usually designed for normal operation mode, which makes it important to consider power consumption during test mode, otherwise the higher power consumption during test mode may cause the circuits being damaged. In this paper, a new approach for the test pattern design of VLSI circuits is presented, the approach defines the weight values of primary inputs of circuits, makes use of both circuit structure information and pseudorandom test generation to produce the test patterns, such that the circuit has lower power consumption when the test patterns are applied to the circuit primary inputs. The experimental results show the approach in this paper can get significant power consumption reduction compared with conventional random test algorithm.

Info:

Periodical:

Solid State Phenomena (Volumes 181-182)

Edited by:

Yuan Ming Huang

Pages:

229-232

DOI:

10.4028/www.scientific.net/SSP.181-182.229

Citation:

Z. L. Pan and L. Chen, "Low Power Test Pattern Design for VLSI Circuits Using Incorporate Pseudorandom and Deterministic Approach", Solid State Phenomena, Vols. 181-182, pp. 229-232, 2012

Online since:

November 2011

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Price:

$35.00

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