Ultra Clean Processing of Semiconductor Surfaces XI

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Authors: Aaron Thean
Abstract: With the continuing growth of data bandwidth, next-generation information technology demands circuit and device scaling to meet performance, form-factor and cost needs. With increase performance and circuit density, reduction in power dissipation has become paramount for both high-performance and low-power applications. In the case of high-performance systems, heat dissipation becomes the thermal bottle neck. Limited by battery, low-power mobile applications ration energy to maintain user multimedia experience while on the move. Lowering supply voltage (Vdd) is becoming the major system enabler to manage the power challenges.
Authors: Yoshihiro Ogawa
Abstract: Several attempts have recently been made to use novel high-k dielectric materials, such as AlxOy, HfxAlyOz, HfxSiyOz, and HfxOy, to improve electrical device characteristics of advanced devices. Moreover, it is becoming increasingly important in the ULSI manufacturing process to suppress contamination by metal or particles from the wafer backside or edge. This paper reviews the wafer backside/edge control technology for suppression of metal contamination.
Authors: Farid Sebaai, Anabela Veloso, Hiroaki Takahashi, Antoine Pacco, Martine Claes, Marc Schaekers, Stefan de Gendt, Paul W. Mertens, Herbert Struyf
Abstract: The industry has diverged into two main approaches for high-k and metal gate (HKMG) integration. One is the so called gate-first. The other is gate-last, also called replacement metal gate (RMG) where the gate electrode is deposited after junctions formation and the high-k gate dielectric is deposited in the beginning of the flow (high-k first-RMG) or just prior to gate electrode deposition (high-k last-RMG) [1-. We can distinguish two RMG process flows called either high-k first or high-k last. In RMG high-k first, poly silicon is removed on top of a TiN etch stop layer whereas on high-k last poly silicon is removed on top of a dummy oxide layer. This dummy oxide has also to be removed in order to redeposit a novel high-k and work function metal (Figure 1).
Authors: Simon Braun, Rita Vos, Andreas Klipp, Martine Claes, Christian Bittner, Johan Albert, Naoto Horiguchi, Herbert Struyf
Abstract: Cleaning photoresist from semiconductor wafers during the transistor formation in the front end of the line (FEOL) becomes more challenging with ever smaller nodes. First of all the resists do become more difficult to clean with decreasing node size, because implantation energy increase and the resist becomes more complex (to comply with the reduced wave length of the laser light for the lithography) at future node sizes. This results in more cross linked / polymerized photoresist, which is harder to (wet) strip. Additionally, the requirements on material compatibility of the cleaning solution increase, as more elements are used to build the transistor less than a monolayer of these materials can be removed during a single cleaning step.
Authors: Jong Seok Lee, Geun Min Choi, Ji Nok Jung, Dong Duk Lee, Gin Yung Hur, Jai Ho Lee, Che Hyuk Chi, Dae Hee Gimm
Abstract: With scaling of ULSI devices, the process temperatures are continuously lowered. The oxide films, which were deposited at low temperature, show fast etching rates during wet etching compared to high temperature films. Also, the etch rates differ largely from other film deposition conditions. In order to overcome these etch rate differences during surface preparation, dry cleaning processes had been introduced where the etch selectivity of the soft oxide films to the thermal oxide are very similar, regardless of the film deposition conditions and the deposition temperature.
Authors: Dan Alvarez Jr, Jeff Spiegelman, Ed Heinlein, Chris Ramos, Russell J. Holmes, Zohreh Shamsi
Abstract: Conventional aqueous wet cleaning methods in semiconductor manufacturing are facing tremendous challenges, with decreasing line widths and high aspects ratio features on the order of a few nanometers. Water and other liquids have surface tensions that frequently prevent complete penetration into nanometer-sized trenches and vias now being fabricated on semiconductor wafers and other substrates. This problem is accentuated by the fact that particle sizes leading to Killer defects are now on the order of 10 nm or less. Nanometer-sized particles can adhere to a surface with a relatively strong force of over a million times its weight. An effective cleaning technique for submicron particle removal will require complete penetration of the device features to surround and dislodge particles, but at the same time not damage the features or etch the surface.
Authors: Min Su Kim, Bong Kyun Kang, Jae Kwan Kim, Byung Kyu Lee, Jin Goo Park
Abstract: Ultraviolet based nanoimprint lithography (UV-NIL) technology is widely used in nanosized fine pattern transfer. NIL, which uses low pressure and low temperature, makes it possible to fabricate 3-dimensional pattern [. So, UV-NIL is one of the techniques with great potential as a new manufacturing process. But, UV-NIL process uses an expensive quartz substrate for transmission of UV light. Therefore, quartz substrate needs to be recycled to reduce the manufacturing cost. Usually, UV-NIL uses UV curable resins, whose chemical bonding and structure could be altered during UV light exposure which would result in crosslinking between the polymers. This UV cured resin with cross-linked structure is very hard to remove from the quartz substrate [. Conventionally, UV cured resin is removed by treating with sulfuric acid-hydrogen peroxide mixture (SPM) followed by ammonium hydroxide-hydrogen peroxide mixture (APM). One of the major drawbacks in using SPM-based treatment is the chemical haze formation and particle contamination on the quartz substrate [. Thus, an alternative cleaning composition will be of interest.
Authors: Tan Yong Siang, Seah Boon Meng, Leong Lup San, Liu Huang, Zainab Ismail, Alex See
Abstract: The salicide (self-aligned silicide) technology involves selective wet etching step of non-reacted metal with respect to metal silicides. It was introduced in MOSFET fabrication due to the increase of the source, drain and gate resistances with the reduction of device dimensions. The introduction of a low resistive silicide layer on these areas has become mandatory to meet device specifications. NiSi has been widely considered for sub-65nm technology nodes due to its low resistivity, low silicon consumption and low formation temperature [1-2]. The two step annealing sequence is common in the industry for nickel silicide application to control the reverse linewidth effect. However, since Ni is the diffusing element in the NiSi reaction, a first high temperature rapid thermal anneal (RTA) will inadvertently result in Ni lateral diffusion under the spacer towards the gate causing electrical shorts. Indeed, a first low temperature anneal could seriously limit the nickel lateral diffusion and prevent this phenomenon. Minimizing thermal budget by means of reducing the temperature has also been proven to lower junction leakage current [3].
Authors: Hiroaki Takahashi, Masayuki Otsuji, Jim Snow, Farid Sebaai, Kenichiro Arai, Masanobu Sato, Soichi Nadahara
Abstract: Since Tetramethylammonium Hydroxide (TMAH) became widely used as a silicon etchant, e.g. the dummy gate removal for gate-last approach (RMG) [1, or Si fin formation on FinFET [, some careful preparations and optimizations have required implementation. These adaptations have involved not only chemical-related issues, but also hardware-related in order to satisfy the necessary process performance.

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